//
//Integrated digital data processing unit by jb/2012
//
module DDPU (	clk1, mdac1, calib1, 
		      mdac2, calib2,
		      mdac3, calib3, 
		      mdac4, calib4,
		      sar, 
		      adc_output );

input 		clk1;
input[1:0]	mdac1;
input[1:0]	mdac2;
input[1:0]	mdac3;
input[1:0]	mdac4;
input[9:0]	calib1;
input[9:0]	calib2;
input[9:0]	calib3;
input[9:0]	calib4;
input[7:0]	sar;
output[11:0]	adc_output;


//design registers
reg[1:0]	mdac1_reg, mdac2_reg, mdac3_reg, mdac4_reg;
reg[11:0]	md1_cor, md1_corr, md2_corr, md3_corr, md4_corr;
reg[7:0]	sar_reg1,sar_reg2;
reg[11:0]	md12_reg, md123_reg, md1234_reg;	
reg[11:0]	adc_output;

//register the MDAC's outputs
always  @(negedge clk1) 
	begin
	 mdac1_reg <= mdac1;
	 mdac3_reg <= mdac3;
	end
	
always  @(posedge clk1) 
	begin
	 mdac2_reg <= mdac2;
	 mdac4_reg <= mdac4;
	end


//apply digital correction
always  @(negedge clk1) 
	begin
	 if (mdac2_reg[1:0]==2'b00)  md2_corr <= 12'b000000000000;
	 else                        md2_corr <= {mdac2_reg,calib2};
	 if (mdac4_reg[1:0]==2'b00)  md4_corr <= 12'b000000000000;
	 else                        md4_corr <= {mdac4_reg,calib4};
	 sar_reg1 <= sar;
	 md2_corr <= md1_cor;
	end
	
always  @(posedge clk1) 
	begin
	 if (mdac1_reg[1:0]==2'b00)  md1_cor  <= 12'b000000000000;
	 else                        md1_cor  <= {mdac1_reg,calib1};
	 if (mdac3_reg[1:0]==2'b00)  md3_corr <= 12'b000000000000;
	 else                        md3_corr <= {mdac3_reg,calib3};
	 sar_reg2 <= sar_reg1;
	end

//form the final adc word
always  @(posedge clk1) 
	begin
	 md12_reg   <= md1_corr   + md2_corr;
	 md1234_reg <= md123_reg  + md3_corr;
	end
	
always  @(negedge clk1) 
	begin
	 md123_reg  <= md12_reg   + md3_corr;
	 adc_output <= md1234_reg + sar_reg2;
	end

endmodule