Analysis & Synthesis report for glink_Rx_test
Wed Jul 27 07:44:49 2005
Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Multiplexer Restructuring Statistics (No Restructuring Performed)
  5. WYSIWYG Cells
  6. General Register Statistics
  7. Hierarchy
  8. Analysis & Synthesis Resource Utilization by Entity
  9. Analysis & Synthesis Equations
 10. Analysis & Synthesis Source Files Read
 11. Analysis & Synthesis Resource Usage Summary
 12. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
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intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
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party's intellectual property, are provided herein.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Jul 27 07:44:49 2005         ;
; Quartus II Version          ; 4.1 Build 208 09/10/2004 SP 2 SJ Full Version ;
; Revision Name               ; glink_Rx_test                                 ;
; Top-level Entity Name       ; glink_Rx_test                                 ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 98                                            ;
; Total pins                  ; 47                                            ;
; Total memory bits           ; 0                                             ;
; Total PLLs                  ; 0                                             ;
+-----------------------------+-----------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                      ;
+--------------------------------------------------------------------+---------------+---------------+
; Option                                                             ; Setting       ; Default Value ;
+--------------------------------------------------------------------+---------------+---------------+
; Device                                                             ; EP1C6Q240C7   ;               ;
; Family name                                                        ; Cyclone       ; Stratix       ;
; Restructure Multiplexers                                           ; Auto          ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off           ; off           ;
; Disk space/compilation speed tradeoff                              ; Normal        ; Normal        ;
; Preserve fewer node names                                          ; On            ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off           ; Off           ;
; Verilog Version                                                    ; Verilog_2001  ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93        ; VHDL93        ;
; Top-level entity name                                              ; glink_Rx_test ; glink_Rx_test ;
; State Machine Processing                                           ; Auto          ; Auto          ;
; NOT Gate Push-Back                                                 ; On            ; On            ;
; Power-Up Don't Care                                                ; On            ; On            ;
; Remove Redundant Logic Cells                                       ; Off           ; Off           ;
; Remove Duplicate Registers                                         ; On            ; On            ;
; Ignore CARRY Buffers                                               ; Off           ; Off           ;
; Ignore CASCADE Buffers                                             ; Off           ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off           ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off           ; Off           ;
; Ignore LCELL Buffers                                               ; Off           ; Off           ;
; Ignore SOFT Buffers                                                ; On            ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off           ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced      ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70            ; 70            ;
; Auto Carry Chains                                                  ; On            ; On            ;
; Auto Open-Drain Pins                                               ; On            ; On            ;
; Remove Duplicate Logic                                             ; On            ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off           ; Off           ;
; Perform gate-level register retiming                               ; Off           ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On            ; On            ;
; Auto ROM Replacement                                               ; On            ; On            ;
; Auto RAM Replacement                                               ; On            ; On            ;
; Auto Shift Register Replacement                                    ; On            ; On            ;
; Auto Clock Enable Replacement                                      ; On            ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On            ; On            ;
; Auto Resource Sharing                                              ; Off           ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off           ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off           ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off           ; Off           ;
+--------------------------------------------------------------------+---------------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed)                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 2:1                ; 16 bits   ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |glink_Rx_test|parity[0]   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 25    ;
; Number of synthesis-generated cells                    ; 73    ;
; Number of WYSIWYG LUTs                                 ; 25    ;
; Number of synthesis-generated LUTs                     ; 46    ;
; Number of WYSIWYG registers                            ; 25    ;
; Number of synthesis-generated registers                ; 48    ;
; Number of cells with combinational logic only          ; 25    ;
; Number of cells with registers only                    ; 27    ;
; Number of cells with combinational logic and registers ; 46    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 71    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 30    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
glink_Rx_test
 |-- lpm_counter:p_word_cnt_rtl_0
      |-- alt_counter_stratix:wysi_counter
 |-- lpm_counter:start_up_cnt_rtl_1
      |-- alt_counter_stratix:wysi_counter


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
; Compilation Hierarchy Node               ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                            ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
; |glink_Rx_test                           ; 98 (73)     ; 73           ; 0           ; 47   ; 0            ; 25 (25)      ; 27 (27)           ; 46 (21)          ; 25 (0)          ; |glink_Rx_test                                                                 ;
;    |lpm_counter:p_word_cnt_rtl_0|        ; 9 (0)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (0)            ; 9 (0)           ; |glink_Rx_test|lpm_counter:p_word_cnt_rtl_0                                    ;
;       |alt_counter_stratix:wysi_counter| ; 9 (9)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 9 (9)           ; |glink_Rx_test|lpm_counter:p_word_cnt_rtl_0|alt_counter_stratix:wysi_counter   ;
;    |lpm_counter:start_up_cnt_rtl_1|      ; 16 (0)      ; 16           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (0)           ; 16 (0)          ; |glink_Rx_test|lpm_counter:start_up_cnt_rtl_1                                  ;
;       |alt_counter_stratix:wysi_counter| ; 16 (16)     ; 16           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (16)          ; 16 (16)         ; |glink_Rx_test|lpm_counter:start_up_cnt_rtl_1|alt_counter_stratix:wysi_counter ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/designs/D0/glink_Rx_test/glink_Rx_test.map.eqn.


+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                ;
+---------------------------------------------------------------------+-----------------+
; File Name                                                           ; Used in Netlist ;
+---------------------------------------------------------------------+-----------------+
; glink_Rx_test.vhd                                                   ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf         ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_constant.inc        ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/alt_counter_stratix.tdf ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/stratix_lcell.inc       ; yes             ;
+---------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 98      ;
; Total combinational functions     ; 71      ;
; Total 4-input functions           ; 36      ;
; Total 3-input functions           ; 0       ;
; Total 2-input functions           ; 5       ;
; Total 1-input functions           ; 25      ;
; Total 0-input functions           ; 5       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 73      ;
; Total logic cells in carry chains ; 25      ;
; I/O pins                          ; 47      ;
; Maximum fan-out node              ; strbout ;
; Maximum fan-out                   ; 55      ;
; Total fan-out                     ; 399     ;
; Average fan-out                   ; 2.75    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Full Version
    Info: Processing started: Wed Jul 27 07:44:38 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off glink_Rx_test -c glink_Rx_test
Info: Found 2 design units, including 1 entities, in source file glink_Rx_test.vhd
    Info: Found design unit 1: glink_Rx_test-rtl
    Info: Found entity 1: glink_Rx_test
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: p_word_cnt[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: start_up_cnt[0]~0
Info: Found 1 design units, including 1 entities, in source file ../../../quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file ../../../quartus41/libraries/megafunctions/alt_counter_stratix.tdf
    Info: Found entity 1: alt_counter_stratix
Warning: Output pins are stuck at VCC or GND
    Warning: Pin flagsel stuck at GND
    Warning: Pin m20sel stuck at VCC
    Warning: Pin div0 stuck at GND
    Warning: Pin div1 stuck at GND
    Warning: Pin sd1 stuck at GND
Info: Implemented 145 device resources after synthesis - the final resource count might be different
    Info: Implemented 30 input pins
    Info: Implemented 17 output pins
    Info: Implemented 98 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Wed Jul 27 07:44:49 2005
    Info: Elapsed time: 00:00:10


