/*
 *	m5272.h -- Motorola Coldfire 5272 Support
 *
 *	(C) Copyright 2001, Key Technology (http://www.keyww.com)
 */

#ifndef	m5272_h
#define	m5272_h

/*
 *	Define the base address of the UARTS within the MBAR address
 *	space.
 */
#define	MCFUART_BASE1		0x100		/* Base address of UART1 */
#define	MCFUART_BASE2		0x140		/* Base address of UART2 */

/*
 *	Define master clock frequency of our 5272.
 */

#ifndef MCF_CLK
#define	MCF_CLK		66000000
#endif

/*
 * Place to put internal registers
 */

#define	MCF_MBAR	0x10000000

#define mbar_readLong(x)		*((volatile unsigned long *) (MCF_MBAR + x))
#define mbar_writeLong(x,y)		*((volatile unsigned long *) (MCF_MBAR + x)) = y
#define mbar_writeShort(x,y)	*((volatile unsigned short *) (MCF_MBAR + x)) = y
#define mbar_writeByte(x,y)		*((volatile unsigned char *) (MCF_MBAR + x)) = y

/*
 * Size of internal RAM
 */
#define INT_RAM_SIZE 4096

/*
 *	Define the 5272 SIM register set addresses.
 */
#define	MCFSIM_SCR		0x04		/* System Configuration */
#define	MCFSIM_SPR		0x06		/* System Protection */
#define	MCFSIM_ICR1		0x20		/* Intr Ctrl reg 1 (r/w) */
#define	MCFSIM_ICR2		0x24		/* Intr Ctrl reg 2 (r/w) */
#define	MCFSIM_ICR3		0x28		/* Intr Ctrl reg 3 (r/w) */
#define	MCFSIM_ICR4		0x2c		/* Intr Ctrl reg 4 (r/w) */

#define	MCFSIM_PITR		0x34		/* Programmable Interrupt Transition */
#define	MCFSIM_PIWR		0x38		/* Programmable Interrupt Wakeup */
#define	MCFSIM_PIVR		0x3F		/* Programmable Interrupt Vector */

#define	MCFSIM_PACNT	0x80		/* Port A Control (r/w) */
#define	MCFSIM_PADDR	0x84		/* Port A Direction (r/w) */
#define	MCFSIM_PADAT	0x86		/* Port A Value (r/w) */
#define	MCFSIM_PBCNT	0x88		/* Port B Control */
#define	MCFSIM_PBDDR	0x8C		/* Port B Direction */
#define	MCFSIM_PBDAT	0x8E		/* Port B Value */
#define	MCFSIM_PDCNT	0x98		/* Port D Control */

#define	MCFSIM_CSBR0	0x40		/* CS 0 Base reg (r/w) */
#define	MCFSIM_CSOR0	0x44		/* CS 0 Option reg (r/w) */
#define	MCFSIM_CSBR1	0x48		/* CS 1 Base reg (r/w) */
#define	MCFSIM_CSOR1	0x4c		/* CS 1 Option reg (r/w) */
#define	MCFSIM_CSBR2	0x50		/* CS 2 Base reg (r/w) */
#define	MCFSIM_CSOR2	0x54		/* CS 2 Option reg (r/w) */
#define	MCFSIM_CSBR3	0x58		/* CS 3 Base reg (r/w) */
#define	MCFSIM_CSOR3	0x5c		/* CS 3 Option reg (r/w) */
#define	MCFSIM_CSBR4	0x60		/* CS 4 Base reg (r/w) */
#define	MCFSIM_CSOR4	0x64		/* CS 4 Option reg (r/w) */
#define	MCFSIM_CSBR5	0x68		/* CS 5 Base reg (r/w) */
#define	MCFSIM_CSOR5	0x6c		/* CS 5 Option reg (r/w) */
#define	MCFSIM_CSBR6	0x70		/* CS 6 Base reg (r/w) */
#define	MCFSIM_CSOR6	0x74		/* CS 6 Option reg (r/w) */
#define	MCFSIM_CSBR7	0x78		/* CS 7 Base reg (r/w) */
#define	MCFSIM_CSOR7	0x7c		/* CS 7 Option reg (r/w) */

#define MCFSIM_PWCR0	0xc0		// PWM Control Register 0
#define MCFSIM_PWCR1	0xc4		// PWM Control Register 0
#define MCFSIM_PWCR2	0xc8		// PWM Control Register 0
#define MCFSIM_PWWR0	0xd0		// PWM Pulse Width Register 0
#define MCFSIM_PWWR1	0xd4		// PWM Pulse Width Register 0
#define MCFSIM_PWWR2	0xd8		// PWM Pulse Width Register 0

#define MCFSIM_SDCR		0x180		/* SDRAM Control Register */
#define MCFSIM_SDTR		0x184		/* SDRAM Control Register */

#endif	/* m5272_h */