/****************************************************************************/

/*
 *	m5307.h -- Motorola Coldfire 5307 CPU Support.
 *
 *	(C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
 */

/****************************************************************************/
#ifndef	m5307_h
#define	m5307_h
/****************************************************************************/

/*
 *	Define the base address of the UARTS within the MBAR address
 *	space.
 */
#define MCFUART_BASE1		0x1c0           /* Base address of UART1 */
#define MCFUART_BASE2		0x200           /* Base address of UART2 */    

/*
 *	Define master clock frequency of our 5307.
 */
#define	MCF_CLK		45000000

/*
 *	The board memory map is set up as follows:
 *
 *	0x00000000  --  SDRAM (operational memory - 4 or 16 Mb)
 *	0x10000000  --  MBAR (5307 SIM module peripherals)
 *	0x20000000  --  RAMBAR (5307 internal SRAM - 4k)
 *	0x30400000  --  LED bank (CS2)
 *	0x30600000  --  LAN (smc91c96 ethernet (CS3)
 *	0x50000000  --  PCI interface (CS1)
 *	0xf0000000  --  FLASH (1Mb) (CS0)
 */
#define	MCF_MBAR	0x10000000


/*
 * Size of internal RAM
 */

#define INT_RAM_SIZE 4096

/*
 *	Define the 5307 SIM register set addresses.
 */
#define	MCFSIM_SIMR		0x03		/* SIM Config reg (r/w) */
#define	MCFSIM_ICR0		0x4c		/* Intr Ctrl reg 0 (r/w) */
#define	MCFSIM_ICR1		0x4d		/* Intr Ctrl reg 1 (r/w) */
#define	MCFSIM_ICR2		0x4e		/* Intr Ctrl reg 2 (r/w) */
#define	MCFSIM_ICR3		0x4f		/* Intr Ctrl reg 3 (r/w) */
#define	MCFSIM_ICR4		0x50		/* Intr Ctrl reg 4 (r/w) */
#define	MCFSIM_ICR5		0x51		/* Intr Ctrl reg 5 (r/w) */
#define	MCFSIM_ICR6		0x52		/* Intr Ctrl reg 6 (r/w) */
#define	MCFSIM_ICR7		0x53		/* Intr Ctrl reg 7 (r/w) */
#define	MCFSIM_ICR8		0x54		/* Intr Ctrl reg 8 (r/w) */
#define	MCFSIM_ICR9		0x55		/* Intr Ctrl reg 9 (r/w) */
#define	MCFSIM_ICR10		0x56		/* Intr Ctrl reg 10 (r/w) */
#define	MCFSIM_ICR11		0x57		/* Intr Ctrl reg 11 (r/w) */

#define MCFSIM_IPR		0x40		/* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR		0x44		/* Interrupt Mask reg (r/w) */

#define	MCFSIM_RSR		0x00		/* Reset Status reg (r/w) */
#define	MCFSIM_SYPCR		0x01		/* System Protection reg (r/w)*/
#define	MCFSIM_SWIVR		0x02		/* SW Watchdog intr reg (r/w) */
#define	MCFSIM_SWSR		0x03		/* SW Watchdog service (r/w) */
#define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */

#define	MCFSIM_PADDR		0x244		/* Parallel Direction (r/w) */
#define	MCFSIM_PADAT		0x248		/* Parallel Port Value (r/w) */

#define MCFSIM_CSAR0		0x80		/* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0		0x84		/* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0		0x8a		/* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1		0x8c		/* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1		0x90		/* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1		0x96		/* CS 1 Control reg (r/w) */

#define MCFSIM_CSBAR		0x98		/* CS Base Address reg (r/w) */
#define MCFSIM_CSBAMR		0x9c		/* CS Base Mask reg (r/w) */
#define MCFSIM_CSMR2		0x9e		/* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2		0xa2		/* CS 2 Control reg (r/w) */
#define MCFSIM_CSMR3		0xaa		/* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */
#define MCFSIM_CSMR4		0xb6		/* CS 4 Mask reg (r/w) */
#define MCFSIM_CSCR4		0xba		/* CS 4 Control reg (r/w) */
#define MCFSIM_CSMR5		0xc2		/* CS 5 Mask reg (r/w) */
#define MCFSIM_CSCR5		0xc6		/* CS 5 Control reg (r/w) */
#define MCFSIM_CSMR6		0xce		/* CS 6 Mask reg (r/w) */
#define MCFSIM_CSCR6		0xd2		/* CS 6 Control reg (r/w) */
#define MCFSIM_CSMR7		0xda		/* CS 7 Mask reg (r/w) */
#define MCFSIM_CSCR7		0xde		/* CS 7 Control reg (r/w) */

#define MCFSIM_DCR		0x100		/* DRAM Control reg (r/w) */
#define MCFSIM_DACR0		0x108		/* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0		0x10c		/* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */


/*
 *	Some symbol defines for the above...
 */
#define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
#define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
#define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
#define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
#define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */

/*
 *	Macro to set IMR register. It is 32 bits on the 5307.
 */

#define	mcf_getimr()		\
	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))

#define	mcf_setimr(imr)		\
	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);

/****************************************************************************/
#endif	/* m5307_h */