diff -Nr colilo-20030502-5282/arch/5206e/cache.S colilo-20030502-5282.stuart/arch/5206e/cache.S
3a4
> .global disableCache
14a16,26
> 
> disableCache:
> 	move.l	#0x00000400, %d0		/* Disable and invalidate cache */
> 	movec	%d0, %CACR
> 
> 	/* This takes 31 machine cycles */
> 
> 	move.l  #0x00008020, %d0 		/* Completely disable cache */
> 	movec	%d0, %ACR0
> 	movec	%d0, %ACR1
> 	rts
\ No newline at end of file
diff -Nr colilo-20030502-5282/arch/5249/cache.S colilo-20030502-5282.stuart/arch/5249/cache.S
1a2
> .global disableCache
20a22,33
> disableCache:
> 	move.l	#0x00000400, %d0		/* Disable and invalidate cache */
> 	movec	%d0, %CACR
> 
> 	/* This takes 31 machine cycles */
> 
> 	move.l  #0x00008020, %d0 		/* Completely disable cache */
> 	movec	%d0, %ACR0
> 	movec	%d0, %ACR1
> 	rts
> 
> 
diff -Nr colilo-20030502-5282/arch/5272/cache.S colilo-20030502-5282.stuart/arch/5272/cache.S
1a2
> .global disableCache
9a11,21
> 
> disableCache:
> 	move.l	#0x00000400, %d0		/* Disable and invalidate cache */
> 	movec	%d0, %CACR
> 
> 	/* This takes 31 machine cycles */
> 
> 	move.l  #0x00008020, %d0 		/* Completely disable cache */
> 	movec	%d0, %ACR0
> 	movec	%d0, %ACR1
> 	rts
\ No newline at end of file
diff -Nr colilo-20030502-5282/arch/5282/arch.h colilo-20030502-5282.stuart/arch/5282/arch.h
16,17c16
< //#define	MCFUART_BASE1		0x240		/* Base address of UART1 */
< #define	MCFUART_BASE1		0x200		/* allow download on same port as console */
---
> #define	MCFUART_BASE1		0x240		/* Base address of UART1 */
21,33d19
<  *	Define master clock frequency of our 5282.
<  */
< 
< #ifndef MCF_CLK
< //#define	MCF_CLK			64000000	//66000000
< #define	MCF_CLK			32000000	//33000000
< #endif
< 
< // FIXME: needs to move to platform specific include
< // start of SDRAM memory space
< #define MCF_MEMBASE  0x80000000
< 
< /*
diff -Nr colilo-20030502-5282/arch/5282/cache.S colilo-20030502-5282.stuart/arch/5282/cache.S
1a2
> .global disableCache
9a11,21
> 
> disableCache:
> 	move.l	#0x00000400, %d0		/* Disable and invalidate cache */
> 	movec	%d0, %CACR
> 
> 	/* This takes 31 machine cycles */
> 
> 	move.l  #0x00008020, %d0 		/* Completely disable cache */
> 	movec	%d0, %ACR0
> 	movec	%d0, %ACR1
> 	rts
diff -Nr colilo-20030502-5282/arch/5307/cache.S colilo-20030502-5282.stuart/arch/5307/cache.S
1a2
> .global disableCache
13a15,25
> 
> disableCache:
> 	move.l	#0x00000400, %d0		/* Disable and invalidate cache */
> 	movec	%d0, %CACR
> 
> 	/* This takes 31 machine cycles */
> 
> 	move.l  #0x00008020, %d0 		/* Completely disable cache */
> 	movec	%d0, %ACR0
> 	movec	%d0, %ACR1
> 	rts
diff -Nr colilo-20030502-5282/boot.S colilo-20030502-5282.stuart/boot.S
54c54
< 
---
> .extern disableCache
197a198
>  * 	Moved to cache.S under arch Stuart Wood
200,209c201,210
< disableCache:
< 	move.l	#0x00000400, %d0		/* Disable and invalidate cache */
< 	movec	%d0, %CACR
< 
< 	/* This takes 31 machine cycles */
< 
< 	move.l  #0x00008020, %d0 		/* Completely disable cache */
< 	movec	%d0, %ACR0
< 	movec	%d0, %ACR1
< 	rts
---
> //disableCache:
> //	move.l	#0x00000400, %d0		/* Disable and invalidate cache */
> //	movec	%d0, %CACR
> //
> //	/* This takes 31 machine cycles */
> //
> //	move.l  #0x00008020, %d0 		/* Completely disable cache */
> //	movec	%d0, %ACR0
> //	movec	%d0, %ACR1
> //	rts
diff -Nr colilo-20030502-5282/main.c colilo-20030502-5282.stuart/main.c
29c29
< #include "arch.h"      /* Board definitions: we need MCF_MEMBASE from this file */
---
> #include "board.h"
62c62
< 
---
> extern void _portToggle(void);
280c280
< 		enableCache();
---
> //		enableCache();
diff -Nr colilo-20030502-5282/Makefile colilo-20030502-5282.stuart/Makefile
17a18,19
> # 5282		Motorola		M8282
> # 5282		Motorola		M5282Lite
21c23
< BOARD = M5282
---
> BOARD = M5282Lite
95c97
< CFLAGS += -Os -g -fno-builtin -I$(ARCH_DIR)
---
> CFLAGS += -Os -g -fno-builtin -I$(SOURCE_DIR) -I$(ARCH_DIR) -I$(VENDOR_DIR) 
diff -Nr colilo-20030502-5282/misc.c colilo-20030502-5282.stuart/misc.c
100c100
< static unsigned long free_mem_end_ptr = ((long) &_ebss) + (512 * 1024);
---
> static unsigned long free_mem_end_ptr = ((long) &_ebss) + (3072 * 1024);
diff -Nr colilo-20030502-5282/vendors/Motorola/M5282/board.c colilo-20030502-5282.stuart/vendors/Motorola/M5282/board.c
8,42c8
< #include "arch.h"
< #include "mcfuart.h"
< 
< /*
<  * Generic M5282 board setup that supports:
<  * - SDRAM
<  * - internal SRAM
<  * - internal flash
<  * - CS0: external Flash
<  *
<  *  !!! assume that colilo is running from internal flash !!!
<  *  
<  * - UART0: download/command
<  * - UART1: debug
<  *
<  * Memory Map
<  * addr      , size       : desc
<  * 0x00000000, 0x00080000 : internal flash (512KB)
<  * 0x10000000, 0x00010000 : internal SRAM (64KB)
<  * 0x40000000, 0x10000000 : IPSBAR peripheral system base addr (1GB)
<  * 0x80000000, 0x00400000 : SDRAM (128MB max)
<  * 0x90000000, 0x00200000 : CS0 external flash (16MB max)
<  * 
<  */
< 
< // NOTE: all areas/sizes must be integer multiples of 64K
< #define MM_FLASH_BASE	0x00000000	//HW default
< #define MM_SRAM_BASE	0x20010000	//colilo default
< #define MM_SRAM_SIZE	0x00010000	//64KB
< #define MM_IPSBAR_BASE	0x40000000	//HW default
< #define MM_SDRAM_BASE	0x80000000
< #define MM_SDRAM_SIZE	0x01000000	//16MB
< #define MM_CS0_BASE	0x90000000
< #define MM_CS0_SIZE	0x00200000	//2MB
< 
---
> #include "board.h"
diff -Nr colilo-20030502-5282/vendors/Motorola/M5282/board.h colilo-20030502-5282.stuart/vendors/Motorola/M5282/board.h
0a1,53
> /*
>  *	board.h -- Generic Motorola Coldfire 5282 Board Support
>  *
>  *	Copyright 2003, Plentovich Design Services (www.plentovichdesign.com)
>  * 	- ported from .../M5272C3/board.c
>  */
> 
> #include "arch.h"
> #include "mcfuart.h"
> 
> /*
>  * Generic M5282 board setup that supports:
>  * - SDRAM
>  * - internal SRAM
>  * - internal flash
>  * - CS0: external Flash
>  *
>  *  !!! assume that colilo is running from internal flash !!!
>  *  
>  * - UART0: download/command
>  * - UART1: debug
>  *
>  * Memory Map
>  * addr      , size       : desc
>  * 0x00000000, 0x00080000 : internal flash (512KB)
>  * 0x10000000, 0x00010000 : internal SRAM (64KB)
>  * 0x40000000, 0x10000000 : IPSBAR peripheral system base addr (1GB)
>  * 0x80000000, 0x00400000 : SDRAM (128MB max)
>  * 0x90000000, 0x00200000 : CS0 external flash (16MB max)
>  * 
>  */
> 
> // NOTE: all areas/sizes must be integer multiples of 64K
> #define MM_FLASH_BASE	0x00000000	//HW default
> #define MM_SRAM_BASE	0x20010000	//colilo default
> #define MM_SRAM_SIZE	0x00010000	//64KB
> #define MM_IPSBAR_BASE	0x40000000	//HW default
> #define MM_SDRAM_BASE	0x00100000
> #define MM_SDRAM_SIZE	0x01000000	//16MB
> #define MM_CS0_BASE	0x90000000
> #define MM_CS0_SIZE	0x00200000	//2MB
> 
> // start of SDRAM memory space
> #define MCF_MEMBASE	MM_SDRAM_BASE
> 
> /*
>  *	Define master clock frequency of our 5282.
>  */
> 
> #ifndef MCF_CLK
> //#define	MCF_CLK			64000000	//66000000
> #define	MCF_CLK			32000000	//33000000
> #endif
\ No newline at end of file
diff -Nr colilo-20030502-5282/vendors/Motorola/M5282Lite/board.c colilo-20030502-5282.stuart/vendors/Motorola/M5282Lite/board.c
0a1,159
> /*
>  *	board.c -- Generic Motorola Coldfire 5282 Board Support
>  *
>  *	Copyright 2003, Plentovich Design Services (www.plentovichdesign.com)
>  * 	- ported from .../M5272C3/board.c
>  */
> #include "board.h"
> 
> char	ident[] = "Freescale M5282Lite";
> char	copyright[] = "(C) 2003, Plentovich Design Services";
> 
> extern unsigned int downloadPort;
> extern unsigned int image_size;
> extern unsigned char *xfer_addr;
> extern unsigned char *down_addr;
> extern unsigned char *dest_addr;
> extern unsigned char *source_addr;
> 
> extern unsigned long consoleBase;
> 
> void configureConsole()
> {
> 	consoleBase = MCFUART_BASE0;
> 	configureSerial(consoleBase, 19200, MCF_CLK);
> }
> 
> void configureAuxSerial()
> {
> 	configureSerial(MCFUART_BASE1, 19200, MCF_CLK);
> }
> 
> void setLED()
> {	
> };
> 
> void setImageParams()
> {
> 	downloadPort = 1;
> 	image_size = 0x000C0000; // 768K
> 	source_addr = (unsigned char *)(MM_CS0_BASE + 0x40000);    //leaves it on top of dBug
> 	down_addr = (unsigned char *)(MM_SDRAM_BASE + 0x10000);
> 	xfer_addr = (unsigned char *)(MM_SDRAM_BASE + 0x10000);
> 	dest_addr = (unsigned char *)(MM_SDRAM_BASE + 0x10000);
> }
> 
> void setupBoard()
> {
> 	unsigned long temp;
> 	volatile unsigned char	*mbar;
> 	mbar = (volatile unsigned char *) MCF_MBAR;
> 
> 	// disable SW WDT
> 	// !!! assume that supervisor bit is set !!!
> 	mbar_writeShort(MCF_WTM_WCR, 0);
> 
> 	// setup PLL clock to 66MHz
> 	// !!! assume that supervisor bit is set !!!
> 	mbar_writeShort(MCF_SYNCR, 0x2000);	//64MHz	
> //	mbar_writeShort(MCF_SYNCR, 0x2100);	//eval board must run at 32MHz!!!
> //	mbar_writeShort(MCF_SYNCR, 0x1100);	//eval board must run at 24MHz!!!
> 
> 	// CS0: FLASH
> 	mbar_writeLong(MCF_CSMR0, ((MM_CS0_SIZE - 1) & 0xffff0000));
> 	mbar_writeShort(MCF_CSAR0, (MM_CS0_BASE >> 16));
> 	//  external flash settings
> 	//  ws = 0xf
> 	//  aa = 1
> 	//  ps = 0x2
> 	//  bem = 1
> 	//  bstr = 0
> 	//  bstw = 0
> 	mbar_writeShort(MCF_CSCR0, 0x3da0);
> 	mbar_writeLong(MCF_CSMR0, (((MM_CS0_SIZE - 1) & 0xffff0000) | MCF_CSMR_VALID));
> 
> 	// CS1 - CS6 are unused (just mark invalid)
> 	mbar_writeLong(MCF_CSMR1, 0);
> 	mbar_writeLong(MCF_CSMR2, 0);
> 	mbar_writeLong(MCF_CSMR3, 0);
> 	mbar_writeLong(MCF_CSMR4, 0);
> 	mbar_writeLong(MCF_CSMR5, 0);
> 	mbar_writeLong(MCF_CSMR6, 0);
> 
> 	// configure GPIO for UART signals
> 	mbar_writeByte(MCF_PUAPAR, 0x0f);
> 	
> }
> 
> void setupDRAM()
> {
> 	volatile unsigned char *mbar = (unsigned char *)MCF_MBAR;
> 	unsigned long dacr0;
> 	unsigned long dmr0;
> 	int i;
> 
> 	// SDRAM (SDCS0)
> 	// settings for Micron 48LC4M16A2-75 SDRAMs (two configured as 16M x 32bit x 4bank)
> 	// casl = 0x1
> 	// cbm = 0x3
> 	// ps = 0x0
> //	dacr0 = ((MM_SDRAM_BASE & 0xffff0000) | 0x1300);	//CAS 2
> 	dacr0 = ((MM_SDRAM_BASE & 0xffff0000) | 0x2300);	//CAS 3
> 	// wp = 0
> 	// amx = 0x00
> 	dmr0 = ((MM_SDRAM_SIZE - 1) & 0xfffc0000) | 0x01;	//16MB address range
> //	dmr0 = 0x00fc0001;	//16MB address range
> 	
> 	// Power Up Sequence
> 	// wait 100uS
> 	for (i=0; i<100; i++)
> 	{
> 		asm("nop");
> 	}
> 	// NOTE: refresh calc for 4096 row SDRAM
> 	// ((64ms / (1/PLLCLK)) / 4096 rows) = bus_clocks
> 	// RC = (bus_clocks / 16) - 1
> 	mbar_writeShort(MCF_DCR, 0x023f);	// 64ms = 1031 bus clocks @ 66MHz
> //	mbar_writeShort(MCF_DCR, 0x001e);	// 64ms = 500 bus clocks @ 32MHz
> //	mbar_writeShort(MCF_DCR, 0x0016);	// 64ms = 375 bus clocks @ 24MHz
> 	mbar_writeLong(MCF_DACR0, dacr0);
> 	mbar_writeLong(MCF_DMR0, dmr0);
> 
> 	// Precharge Sequence	
> 	// issue PALL command with dummy access in SDRAM
> 	mbar_writeLong(MCF_DACR0, (dacr0 | MCF_DACR_IP));
> 	// write to block in initiate precharge
> 	*((volatile unsigned long *)MM_SDRAM_BASE) = 0;
> 	// wait trp (30ns)
> 	for (i=0; i<5; i++)
> 	{
> 		asm("nop");
> 	}
> 
> 	// Refresh Sequence
> 	// enable refresh
> 	dacr0 |= MCF_DACR_RE;
> 	mbar_writeLong(MCF_DACR0, dacr0);	
> 	// wait for 8 refresh cycles (8 * 64ms)
> 	for (i=0; i<512000; i++)
> 	{
> 		asm("nop");
> 	}
> 
> 	// Mode Register Init Sequence	
> 	// issue MRS command with MRS value as address of access in SDRAM
> 	// mrs command
> 	// wb = 0
> 	// op mode = 0
> 	// casl = 2
> 	// bt = 0
> 	// blen = 0 (set SDRAM burst length to 1 so that 5282 can control burst length)
> 	// (expected SDRAM mode register value 0x0020 --> maps to address value 0x00400)
> //	dmr0 = 0x00c00000;
> //	mbar_writeLong(MCF_DMR0, dmr0);
> 	dacr0 |= MCF_DACR_IMRS;
> 	mbar_writeLong(MCF_DACR0, dacr0);
> //	*((volatile unsigned long *)((MM_SDRAM_BASE & 0xfff00000) | 0x00400)) = 0;	//CAS 2
> 	*((volatile unsigned long *)((MM_SDRAM_BASE & 0xfff00000) | 0x00c00)) = 0;	//CAS 3
> 	
> }
diff -Nr colilo-20030502-5282/vendors/Motorola/M5282Lite/board.h colilo-20030502-5282.stuart/vendors/Motorola/M5282Lite/board.h
0a1,57
> /*
>  *	board.h -- Freescale Coldfire M5282Lite Board Support
>  *
>  *	Modified Stuart Wood	Nov. 2004
>  *
>  *	Copyright 2003, Plentovich Design Services (www.plentovichdesign.com)
>  * 	- ported from .../M5272C3/board.c
>  */
> 
> #include "arch.h"
> #include "mcfuart.h"
> 
> /*
>  * Freescale M5282Lite board setup that supports:
>  * - SDRAM
>  * - internal SRAM
>  * - internal flash
>  * - CS0: external Flash
>  *
>  *  !!! assume that colilo is running from internal flash !!!
>  *  
>  * - UART0: download/command
>  * - UART1: debug
>  *
>  * Memory Map
>  * addr      , size       : desc
>  * 0x00000000, 0x00080000 : internal flash (512KB)
>  * 0x10000000, 0x01000000 : SDRAM (16MB)
>  * 0x20000000, 0x00010000 : internal SRAM (64KB)
>  * 0x40000000, 0x10000000 : IPSBAR peripheral system base addr (1GB)
>  * 0x90000000, 0x00200000 : CS0 external flash (16MB max)
>  * 
>  */
> 
> // NOTE: all areas/sizes must be integer multiples of 64K
> #define MM_FLASH_BASE	0x00000000	//HW default
> //#define MM_SDRAM_BASE	0x00100000
> #define MM_SDRAM_BASE	0x10000000
> #define MM_SDRAM_SIZE	0x01000000	//16MB
> //#define MM_SRAM_BASE	0x20010000	//colilo default
> #define MM_SRAM_BASE	0x20000000	//colilo default
> #define MM_SRAM_SIZE	0x00010000	//64KB
> #define MM_IPSBAR_BASE	0x40000000	//HW default
> #define MM_CS0_BASE	0x90000000
> #define MM_CS0_SIZE	0x00200000	//2MB
> 
> // start of SDRAM memory space
> #define MCF_MEMBASE	MM_SDRAM_BASE
> 
> /*
>  *	Define master clock frequency of our 5282.
>  */
> 
> #ifndef MCF_CLK
> #define	MCF_CLK			64000000	//66000000
> //#define	MCF_CLK			32000000	//33000000
> #endif
\ No newline at end of file
diff -Nr colilo-20030502-5282/vendors/Motorola/M5282Lite/flash.ld colilo-20030502-5282.stuart/vendors/Motorola/M5282Lite/flash.ld
0a1,33
> 
> MEMORY {
> /*	flash	: ORIGIN = 0x00000000, LENGTH = 0x00008000 */
> 	flash	: ORIGIN = 0x00000000, LENGTH = 0x00080000 
> 		/* Length = 512KB */
> /*	ram 	: ORIGIN = 0x00FC0000, LENGTH = 0x00400000 */
> 		/* last 256Kbytes of sdram */
> 	ram 	: ORIGIN = 0x10C00000, LENGTH = 0x00400000
> 		/* last 4Mbytes of sdram */
> }
> 
> SECTIONS {
> 
>         .text : {
> 		_stext = . ;
>         	*(.text)
> 		*(.rodata)
> 		_etext = . ;
>         } > flash
> 
>         .data : AT (ADDR(.text) + SIZEOF(.text)) {
> 		_sdata = . ;
>         	*(.data)
> 		_edata = . ;
>         } > ram
> 
>         .bss : AT (ADDR(.text) + SIZEOF(.text) + SIZEOF(.data)) {
> 		_sbss = . ;
> 		*(.bss)
> 		*(COMMON)
> 		_ebss = . ;
> 	} > ram
> }
diff -Nr colilo-20030502-5282/vendors/Motorola/M5282Lite/Makefile colilo-20030502-5282.stuart/vendors/Motorola/M5282Lite/Makefile
0a1,3
> colilo.s19:
> 	$(OBJCOPY) --input-target=binary --output-target=srec --adjust-vma 0x00000000 \
> 		$(SOURCE_DIR)/colilo.bin $(SOURCE_DIR)/colilo.s19
diff -Nr colilo-20030502-5282/vendors/Motorola/M5282Lite/ram.ld colilo-20030502-5282.stuart/vendors/Motorola/M5282Lite/ram.ld
0a1,28
> 
> MEMORY {
> 	flash	: ORIGIN = 0x20010000, LENGTH = 0x00008000
> 	ram 	: ORIGIN = 0x004C0000, LENGTH = 0x00040000			/* last 256Kbytes of sdram */
> }
> 
> SECTIONS {
> 
>         .text : {
> 		_stext = . ;
>         	*(.text)
> 		*(.rodata)
> 		_etext = . ;
>         } > flash
> 
>         .data : AT (ADDR(.text) + SIZEOF(.text)) {
> 		_sdata = . ;
>         	*(.data)
> 		_edata = . ;
>         } > ram
> 
>         .bss : AT (ADDR(.text) + SIZEOF(.text) + SIZEOF(.data)) {
> 		_sbss = . ;
> 		*(.bss)
> 		*(COMMON)
> 		_ebss = . ;
> 	} > ram
> }