Release 6.1.03i - Bitgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Loading device database for application Bitgen from file "phlom.ncd". "phlom" is an NCD, version 2.38, device xc2v1000, package bg575, speed -4 Loading device for application Bitgen from file '2v1000.nph' in environment C:/programs/Xilinx. The STEPPING level for this design is 0. Opened constraints file phlom.pcf. Wed Oct 11 16:37:19 2006 C:/programs/Xilinx/bin/nt/bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g PowerdownPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutDown:Disable -g DisableBandgap:No -g FreezeDCI:Yes -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No phlom.ncd Summary of Bitgen Options: +----------------------+----------------------+ | Option Name | Current Setting | +----------------------+----------------------+ | Compress | (Not Specified)* | +----------------------+----------------------+ | Readback | (Not Specified)* | +----------------------+----------------------+ | CRC | Enable** | +----------------------+----------------------+ | DebugBitstream | No** | +----------------------+----------------------+ | ConfigRate | 4** | +----------------------+----------------------+ | StartupClk | Cclk** | +----------------------+----------------------+ | DCMShutdown | Disable** | +----------------------+----------------------+ | DisableBandgap | No** | +----------------------+----------------------+ | CclkPin | Pullup** | +----------------------+----------------------+ | DonePin | Pullup** | +----------------------+----------------------+ | HswapenPin | Pullup* | +----------------------+----------------------+ | M0Pin | Pullup** | +----------------------+----------------------+ | M1Pin | Pullup** | +----------------------+----------------------+ | M2Pin | Pullup** | +----------------------+----------------------+ | PowerdownPin | Pullup** | +----------------------+----------------------+ | ProgPin | Pullup** | +----------------------+----------------------+ | TckPin | Pullup** | +----------------------+----------------------+ | TdiPin | Pullup** | +----------------------+----------------------+ | TdoPin | Pullup** | +----------------------+----------------------+ | TmsPin | Pullup** | +----------------------+----------------------+ | UnusedPin | Pulldown** | +----------------------+----------------------+ | GWE_cycle | 6** | +----------------------+----------------------+ | GTS_cycle | 5** | +----------------------+----------------------+ | LCK_cycle | NoWait** | +----------------------+----------------------+ | Match_cycle | NoWait | +----------------------+----------------------+ | DONE_cycle | 4** | +----------------------+----------------------+ | Persist | No* | +----------------------+----------------------+ | DriveDone | No** | +----------------------+----------------------+ | DonePipe | No** | +----------------------+----------------------+ | Security | None** | +----------------------+----------------------+ | UserID | 0xFFFFFFFF** | +----------------------+----------------------+ | ActivateGclk | No* | +----------------------+----------------------+ | ActiveReconfig | No* | +----------------------+----------------------+ | PartialMask0 | (Not Specified)* | +----------------------+----------------------+ | PartialMask1 | (Not Specified)* | +----------------------+----------------------+ | PartialMask2 | (Not Specified)* | +----------------------+----------------------+ | PartialGclk | (Not Specified)* | +----------------------+----------------------+ | PartialLeft | (Not Specified)* | +----------------------+----------------------+ | PartialRight | (Not Specified)* | +----------------------+----------------------+ | Encrypt | No** | +----------------------+----------------------+ | Key0 | pick* | +----------------------+----------------------+ | Key1 | pick* | +----------------------+----------------------+ | Key2 | pick* | +----------------------+----------------------+ | Key3 | pick* | +----------------------+----------------------+ | Key4 | pick* | +----------------------+----------------------+ | Key5 | pick* | +----------------------+----------------------+ | Keyseq0 | M* | +----------------------+----------------------+ | Keyseq1 | M* | +----------------------+----------------------+ | Keyseq2 | M* | +----------------------+----------------------+ | Keyseq3 | M* | +----------------------+----------------------+ | Keyseq4 | M* | +----------------------+----------------------+ | Keyseq5 | M* | +----------------------+----------------------+ | KeyFile | (Not Specified)* | +----------------------+----------------------+ | StartKey | 0* | +----------------------+----------------------+ | StartCBC | pick* | +----------------------+----------------------+ | FreezeDCI | Yes | +----------------------+----------------------+ | IEEE1532 | No* | +----------------------+----------------------+ | Binary | No** | +----------------------+----------------------+ * Default setting. ** The specified setting matches the default setting. Running DRC. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net DS is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net QSPI_SHIFT_CLK is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:523 - Blockcheck: Unexpected DCM connection. The signal on the CLKIN pin of DCM comp XLXI_1285 is not driven by an IOB or BUFGMUX therefore the phase relationship of output clocks to CLKIN cannot be guaranteed. WARNING:DesignRules:522 - Blockcheck: Unexpected DCM feedback loop. The signal XLXN_3300 on the CLKFB pin of DCM comp XLXI_1285 is not driven by an IOB or BUFGMUX therefore the phase relationship of output clocks to CLKIN cannot be guaranteed. WARNING:DesignRules:522 - Blockcheck: Unexpected DCM feedback loop. The signal XLXN_3265 on the CLKFB pin of DCM comp XLXI_1749 is not driven by an IOB or BUFGMUX therefore the phase relationship of output clocks to CLKIN cannot be guaranteed. DRC detected 0 errors and 5 warnings. Creating bit map... Saving bit stream in "phlom.bit". Bitstream generation is complete.