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#
# Xilinx Core Generator version J.30
# Date: Tue Apr 17 17:27:59 2007
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc2v1000
SET devicefamily = virtex2
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Edif
SET package = fg456
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Binary_Counter family Xilinx,_Inc. 6.0
# END Select
# BEGIN Parameters
CSET async_init_value=0
CSET asynchronous_settings=set_and_clear
CSET ce_override_for_load=false
CSET ce_overrides=sync_controls_override_ce
CSET clock_enable=true
CSET component_name=cb16
CSET count_by_value=1
CSET count_style=count_by_constant
CSET count_to_value=MAX
CSET create_rpm=true
CSET load=false
CSET load_sense=active_high
CSET operation=up
CSET output_width=4
CSET restrict_count=false
CSET set_clear_priority=clear_overrides_set
CSET sync_init_value=0
CSET synchronous_settings=none
CSET threshold_0=true
CSET threshold_0_value=D
CSET threshold_1=true
CSET threshold_1_value=F
CSET threshold_early=true
CSET threshold_options=both
# END Parameters
GENERATE
# CRC: 2151301d