/*********************************************************************
* Initialisation Code for ColdFire MCF5235 Processor                 *
**********************************************************************/
// Generated by ColdFire Initialisation Utility 2.8.1
// Wed Aug 30 09:53:19 2006
// External reference frequency is 25.0000 MHz
// Internal bus clock frequency = 75.00 MHz
// Processor core frequency = 150.00 MHz

#include "mcf5xxx.h"
#include "mcf523x.h"

// Declare base address of peripherals area
#define __IPSBAR ((vuint8 *) 0x40000000)

// Function prototypes
void init_main (void);
static void disable_interrupts (void);
static void disable_watchdog_timer (void);
static void disable_cache (void);
static void init_ipsbar (void);
static void init_basics (void);
static void init_clock_config (void);
static void init_sram (void);
static void init_chip_selects (void);
static void init_bus_config (void);
static void init_cache (void);
static void init_eport (void);
static void init_ethernet (void);
static void init_flexcan (void);
static void init_power_management (void);
static void init_qspi (void);
static void init_uarts (void);
static void init_dma_timers (void);
static void init_interrupt_timers (void);
static void init_watchdog_timers (void);
static void init_pin_assignments (void);
static void init_sdram_controller (void);
static void init_interrupt_controller (void);

void inline idle(int i){
	for(;i>0;i--);
}

/*********************************************************************
* init_main - Main entry point for initialisation code               *
**********************************************************************/
void init_main (void)
{
    // Mask all interrupts
    asm("move.l   #0x00002700,%d0");
    asm("move     %d0,%SR");

    // Initialise base address of peripherals, VBR, etc
    init_ipsbar ();
	dprintf("1\n");
	idle(10000);
    init_basics ();
	dprintf("2\n");
	idle(10000);
    init_clock_config ();

    // Disable interrupts, watchdog timer, cache
    disable_interrupts ();
	dprintf("3\n");
	idle(10000);
    disable_watchdog_timer ();
	dprintf("4\n");
	idle(10000);
    disable_cache ();
	dprintf("5\n");
	idle(10000);

    // Initialise individual modules
    init_sram ();
	dprintf("6\n");
	idle(10000);
    init_chip_selects ();
	dprintf("7\n");
	idle(10000);
    init_bus_config ();
	dprintf("8\n");
	idle(10000);
    //init_cache ();
    init_eport ();
	dprintf("9\n");
	idle(10000);
    init_ethernet ();
	dprintf("0\n");
	idle(10000);
    init_flexcan ();
	dprintf("a\n");
	idle(10000);
    init_power_management ();
	dprintf("b\n");
	idle(10000);
    init_qspi ();
	dprintf("c\n");
	idle(10000);
    init_uarts ();
	dprintf("d\n");
	idle(10000);
    init_dma_timers ();
	dprintf("e\n");
	idle(10000);
    init_interrupt_timers ();
	dprintf("f\n");
	idle(10000);
    init_watchdog_timers ();
	dprintf("g\n");
	idle(10000);
    init_pin_assignments ();
	dprintf("h\n");
	idle(10000);

    // Initialise SDRAM controller (must be done after pin assignments)
    init_sdram_controller ();
	dprintf("i\n");
	idle(10000);

    // Initialise interrupt controller
    init_interrupt_controller ();
	dprintf("j\n");
	idle(10000);

//...Write some code here...
//   NOTE: Status register (SR) is currently 0x2700 (All interrupts masked).
//         You must also declare the exception vector table at the address
//         loaded into the VBR.
}

/*********************************************************************
* disable_interrupts - Disable all interrupt sources                 *
**********************************************************************/
static void disable_interrupts (void)
{
    vuint8  *p;
    int     i;

    // Set ICR008-ICR063 to 0x0
    p = (vuint8 *) &MCF_INTC0_ICR8;
    for (i = 8; i <= 63; i++)
        *p++ = 0x0;

    // Set ICR108-ICR163 to 0x0
    p = (vuint8 *) &MCF_INTC1_ICR8;
    for (i = 108; i <= 163; i++)
        *p++ = 0x0;
}

/*********************************************************************
* disable_watchdog_timer - Disable system watchdog timer             *
**********************************************************************/
static void disable_watchdog_timer (void)
{
    // Disable Core Watchdog Timer

    //     CWCR[CWE]       = 0 
    //     CWCR[CWRI]      = 0 
    //     CWCR[CWT]       = 0 
    //     CWCR[CWTA]      = 0 
    //     CWCR[CWTAVAL]   = 0 
    //     CWCR[CWTIF]     = 0 
    MCF_SCM_CWCR = 0;
}

/*********************************************************************
* disable_cache - Disable and invalidate cache                       *
**********************************************************************/
static void disable_cache (void)
{
    //     CACR[CENB]      = 0 
    //     CACR[CDPI]      = 0 
    //     CACR[CFRZ]      = 0 
    //     CACR[CINV]      = 1 
    //     CACR[DISI]      = 0 
    //     CACR[DISD]      = 0 
    //     CACR[INVI]      = 0 
    //     CACR[INVD]      = 0 
    //     CACR[CEIB]      = 0 
    //     CACR[DCM]       = 0 
    //     CACR[DBWE]      = 0 
    //     CACR[DWP]       = 0 
    //     CACR[EUSP]      = 0 
    //     CACR[CLNF]      = 0 
    asm("move.l   #0x01000000,%d0");
    asm("movec    %d0,%CACR");
}

/*********************************************************************
* init_basics - Configuration Information & VBR                      *
**********************************************************************/
static void init_basics (void)
{
    // Transfer size not driven on SIZ[1:0] pins during external cycles
    // Processor Status (PST) and Debug Data (DDATA) functions disabled
    // Bus monitor enabled, timeout = 65536 system clocks
    // Output pads configured for full strength

    //     CCON[LOAD]      = 1 
    //     CCON[SZEN]      = 0 
    //     CCON[PSTEN]     = 0 
    //     CCON[BME]       = 1 
    //     CCON[BMT]       = 0 
    MCF_CCM_CCR = (0x1 << 15) |
                  MCF_CCM_CCR_BME;

    // Exception vector table at $00000000

    //     VBR[BA]         = 0 
    asm("move.l   #0x00000000,%d0");
    asm("movec    %d0,%VBR");
}

/*********************************************************************
* init_clock_config - Clock Module                                   *
**********************************************************************/
static void init_clock_config (void)
{
    // Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
    // MFD = 1, RFD = 0
    // Bus clock frequency = 75.00 MHz
    // Processor clock frequency = 2 x bus clock = 150.00 MHz
    // Frequency Modulation disabled
    // Loss of clock detection disabled
    // Reset/Interrupt on loss of lock disabled

    MCF_FMPLL_SYNCR = 0x01080000;                 // Set RFD=RFD+1 to avoid frequency overshoot
    while ((MCF_FMPLL_SYNSR & 0x08) == 0)         // Wait for PLL to lock
        ;
    MCF_FMPLL_SYNCR = 0x01000000;                 // Set desired RFD
    while ((MCF_FMPLL_SYNSR & 0x08) == 0)         // Wait for PLL to lock
        ;
}

/*********************************************************************
* init_ipsbar - Internal Peripheral System Base Address (IPSBAR)     *
**********************************************************************/
static void init_ipsbar (void)
{
    // Base address of internal peripherals (IPSBAR) = 0x40000000
    //  
    // Note: Processor powers up with IPS base address = 0x40000000
    //       Write to IPS base + 0x00000000 to set new value
    * (vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1; // +1 for Enable
}

/*********************************************************************
* init_chip_selects - Chip Select Module                             *
**********************************************************************/
static void init_chip_selects (void)
{
    // Chip Select 0: 2 MB of Flash at base address $ffe00000
    // Port size = 16 bits
    // Generate internal transfer acknowledge after 15 wait states

    //     CSAR0[BA]       = $ffe0
    MCF_CS_CSAR0 = 0xffe0;

    //     CSMR0[BAM]      = $1f
    //     CSMR0[WP]       = 0 
    //     CSMR0[V]        = 1 
    MCF_CS_CSMR0 = MCF_CS_CSMR_BAM(0x1f) |
                   MCF_CS_CSMR_V;

    //     CSCR0[SRWS]     = 0 
    //     CSCR0[IWS]      = %1111
    //     CSCR0[AA]       = 1 
    //     CSCR0[PS]       = %10
    //     CSCR0[BEM]      = 0 
    //     CSCR0[BSTR]     = 0 
    //     CSCR0[BSTW]     = 0 
    //     CSCR0[SWWS]     = 0 
    MCF_CS_CSCR0 = MCF_CS_CSCR_IWS(0xf) |
                   MCF_CS_CSCR_AA       |
                   MCF_CS_CSCR_PS(0x2);

    // Chip Select 1 disabled (CSMR1[V] = 0)

    //     CSAR1[BA]       = 0 
    MCF_CS_CSAR1 = 0;

    //     CSMR1[BAM]      = 0 
    //     CSMR1[WP]       = 0 
    //     CSMR1[V]        = 0 
    MCF_CS_CSMR1 = 0;

    //     CSCR1[SRWS]     = 0 
    //     CSCR1[IWS]      = 0 
    //     CSCR1[AA]       = 0 
    //     CSCR1[PS]       = 0 
    //     CSCR1[BEM]      = 0 
    //     CSCR1[BSTR]     = 0 
    //     CSCR1[BSTW]     = 0 
    //     CSCR1[SWWS]     = 0 
    MCF_CS_CSCR1 = 0;

    // Chip Select 2 disabled (CSMR2[V] = 0)

    //     CSAR2[BA]       = 0 
    MCF_CS_CSAR2 = 0;

    //     CSMR2[BAM]      = 0 
    //     CSMR2[WP]       = 0 
    //     CSMR2[V]        = 0 
    MCF_CS_CSMR2 = 0;

    //     CSCR2[SRWS]     = 0 
    //     CSCR2[IWS]      = 0 
    //     CSCR2[AA]       = 0 
    //     CSCR2[PS]       = 0 
    //     CSCR2[BEM]      = 0 
    //     CSCR2[BSTR]     = 0 
    //     CSCR2[BSTW]     = 0 
    //     CSCR2[SWWS]     = 0 
    MCF_CS_CSCR2 = 0;

    // Chip Select 3 disabled (CSMR3[V] = 0)

    //     CSAR3[BA]       = 0 
    MCF_CS_CSAR3 = 0;

    //     CSMR3[BAM]      = 0 
    //     CSMR3[WP]       = 0 
    //     CSMR3[V]        = 0 
    MCF_CS_CSMR3 = 0;

    //     CSCR3[SRWS]     = 0 
    //     CSCR3[IWS]      = 0 
    //     CSCR3[AA]       = 0 
    //     CSCR3[PS]       = 0 
    //     CSCR3[BEM]      = 0 
    //     CSCR3[BSTR]     = 0 
    //     CSCR3[BSTW]     = 0 
    //     CSCR3[SWWS]     = 0 
    MCF_CS_CSCR3 = 0;

    // Chip Select 4 disabled (CSMR4[V] = 0)

    //     CSAR4[BA]       = 0 
    MCF_CS_CSAR4 = 0;

    //     CSMR4[BAM]      = 0 
    //     CSMR4[WP]       = 0 
    //     CSMR4[V]        = 0 
    MCF_CS_CSMR4 = 0;

    //     CSCR4[SRWS]     = 0 
    //     CSCR4[IWS]      = 0 
    //     CSCR4[AA]       = 0 
    //     CSCR4[PS]       = 0 
    //     CSCR4[BEM]      = 0 
    //     CSCR4[BSTR]     = 0 
    //     CSCR4[BSTW]     = 0 
    //     CSCR4[SWWS]     = 0 
    MCF_CS_CSCR4 = 0;

    // Chip Select 5 disabled (CSMR5[V] = 0)

    //     CSAR5[BA]       = 0 
    MCF_CS_CSAR5 = 0;

    //     CSMR5[BAM]      = 0 
    //     CSMR5[WP]       = 0 
    //     CSMR5[V]        = 0 
    MCF_CS_CSMR5 = 0;

    //     CSCR5[SRWS]     = 0 
    //     CSCR5[IWS]      = 0 
    //     CSCR5[AA]       = 0 
    //     CSCR5[PS]       = 0 
    //     CSCR5[BEM]      = 0 
    //     CSCR5[BSTR]     = 0 
    //     CSCR5[BSTW]     = 0 
    //     CSCR5[SWWS]     = 0 
    MCF_CS_CSCR5 = 0;

    // Chip Select 6 disabled (CSMR6[V] = 0)

    //     CSAR6[BA]       = 0 
    MCF_CS_CSAR6 = 0;

    //     CSMR6[BAM]      = 0 
    //     CSMR6[WP]       = 0 
    //     CSMR6[V]        = 0 
    MCF_CS_CSMR6 = 0;

    //     CSCR6[SRWS]     = 0 
    //     CSCR6[IWS]      = 0 
    //     CSCR6[AA]       = 0 
    //     CSCR6[PS]       = 0 
    //     CSCR6[BEM]      = 0 
    //     CSCR6[BSTR]     = 0 
    //     CSCR6[BSTW]     = 0 
    //     CSCR6[SWWS]     = 0 
    MCF_CS_CSCR6 = 0;

    // Chip Select 7 disabled (CSMR7[V] = 0)

    //     CSAR7[BA]       = 0 
    MCF_CS_CSAR7 = 0;

    //     CSMR7[BAM]      = 0 
    //     CSMR7[WP]       = 0 
    //     CSMR7[V]        = 0 
    MCF_CS_CSMR7 = 0;

    //     CSCR7[SRWS]     = 0 
    //     CSCR7[IWS]      = 0 
    //     CSCR7[AA]       = 0 
    //     CSCR7[PS]       = 0 
    //     CSCR7[BEM]      = 0 
    //     CSCR7[BSTR]     = 0 
    //     CSCR7[BSTW]     = 0 
    //     CSCR7[SWWS]     = 0 
    MCF_CS_CSCR7 = 0;
}

/*********************************************************************
* init_bus_config - Internal Bus Arbitration                         *
**********************************************************************/
static void init_bus_config (void)
{
    // Use round robin arbitration scheme
    // Assigned priorities (highest first):
    //     Ethernet
    //     DMA Controller
    //     ColdFire Core
    // DMA bandwidth control disabled
    // Park on last active bus master

    //     MPARK[M2_P_EN]  = 0 
    //     MPARK[M3_PRTY]  = %11
    //     MPARK[M2_PRTY]  = %10
    //     MPARK[M0_PRTY]  = 0 
    //     MPARK[M1_PRTY]  = %01
    //     MPARK[FIXED]    = 0 
    //     MPARK[TIMEOUT]  = 0 
    //     MPARK[PRKLAST]  = 0 
    //     MPARK[LCKOUT_TIME] = 0
    MCF_SCM_MPARK = MCF_SCM_MPARK_M3_PRTY(0x3) |
                    MCF_SCM_MPARK_M2_PRTY(0x2) |
                    MCF_SCM_MPARK_M1_PRTY(0x1);
}

/*********************************************************************
* init_cache - Instruction/Data Cache                                *
**********************************************************************/
static void init_cache (void)
{
    // Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache
    // ACR0: Memory region disabled
    // ACR1: Memory region disabled
    // CACR: Don't cache accesses to any memory address

    //     CACR[CENB]      = 1 
    //     CACR[CDPI]      = 0 
    //     CACR[CFRZ]      = 0 
    //     CACR[CINV]      = 0 
    //     CACR[DISI]      = 0 
    //     CACR[DISD]      = 0 
    //     CACR[INVI]      = 0 
    //     CACR[INVD]      = 0 
    //     CACR[CEIB]      = 0 
    //     CACR[DCM]       = 1 
    //     CACR[DBWE]      = 0 
    //     CACR[DWP]       = 0 
    //     CACR[EUSP]      = 0 
    //     CACR[CLNF]      = 0 
    asm("move.l   #0x80000200,%d0");
    asm("movec    %d0,%CACR");

    //     ACR0[BA]        = 0 
    //     ACR0[BAM]       = 0 
    //     ACR0[EN]        = 0 
    //     ACR0[SM]        = 0 
    //     ACR0[CM]        = 0 
    //     ACR0[BWE]       = 0 
    //     ACR0[WP]        = 0 
    asm("move.l   #0x00000000,%d0");
    asm("movec    %d0,%ACR0");

    //     ACR1[BA]        = 0 
    //     ACR1[BAM]       = 0 
    //     ACR1[EN]        = 0 
    //     ACR1[SM]        = 0 
    //     ACR1[CM]        = 0 
    //     ACR1[BWE]       = 0 
    //     ACR1[WP]        = 0 
    asm("move.l   #0x00000000,%d0");
    asm("movec    %d0,%ACR1");
}

/*********************************************************************
* init_eport - Edge Port Module (EPORT)                              *
**********************************************************************/
static void init_eport (void)
{
    // Pins 1-7 configured as GPIO inputs

    //     EPPAR[EPPA7]    = 0 
    //     EPPAR[EPPA6]    = 0 
    //     EPPAR[EPPA5]    = 0 
    //     EPPAR[EPPA4]    = 0 
    //     EPPAR[EPPA3]    = 0 
    //     EPPAR[EPPA2]    = 0 
    //     EPPAR[EPPA1]    = 0 
    MCF_EPORT_EPPAR = 0;

    //     EPDDR[EPDD7]    = 0 
    //     EPDDR[EPDD6]    = 0 
    //     EPDDR[EPDD5]    = 0 
    //     EPDDR[EPDD4]    = 0 
    //     EPDDR[EPDD3]    = 0 
    //     EPDDR[EPDD2]    = 0 
    //     EPDDR[EPDD1]    = 0 
    MCF_EPORT_EPDDR = 0;

    //     EPIER[EPIE7]    = 0 
    //     EPIER[EPIE6]    = 0 
    //     EPIER[EPIE5]    = 0 
    //     EPIER[EPIE4]    = 0 
    //     EPIER[EPIE3]    = 0 
    //     EPIER[EPIE2]    = 0 
    //     EPIER[EPIE1]    = 0 
    MCF_EPORT_EPIER = 0;
}

/*********************************************************************
* init_ethernet - Ethernet Module                                    *
**********************************************************************/
static void init_ethernet (void)
{
    // Received frames sent with broadcast address FFFF FFFF FFFF accepted
    // Transceiver uses 10/100Mbps Media Independent Interface
    // Maximum frame length = 1518 bytes
    // All interrupt sources are disabled (masked)

    //     RCR0[MAX_FL]    = $5ee
    //     RCR0[FCE]       = 0 
    //     RCR0[BC_REJ]    = 0 
    //     RCR0[PROM]      = 0 
    //     RCR0[MII_MODE]  = 1 
    //     RCR0[DRT]       = 0 
    //     RCR0[LOOP]      = 0 
    MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL(0x5ee) |
                  MCF_FEC_RCR_MII_MODE;

    //     TCR0[RFC_PAUSE] = 0 
    //     TCR0[TFC_PAUSE] = 0 
    //     TCR0[FDEN]      = 1 
    //     TCR0[HBC]       = 0 
    //     TCR0[GTS]       = 0 
    MCF_FEC_TCR = MCF_FEC_TCR_FDEN;

    //     EIMR0[HBERR]    = 0 
    //     EIMR0[BABR]     = 0 
    //     EIMR0[BABT]     = 0 
    //     EIMR0[GRA]      = 0 
    //     EIMR0[TXF]      = 0 
    //     EIMR0[TXB]      = 0 
    //     EIMR0[RXF]      = 0 
    //     EIMR0[RXB]      = 0 
    //     EIMR0[MII]      = 0 
    //     EIMR0[EBERR]    = 0 
    //     EIMR0[LC]       = 0 
    //     EIMR0[RL]       = 0 
    //     EIMR0[UN]       = 0 
    MCF_FEC_EIMR = 0;

    //     FRSR0[R_FSTART] = $40
    MCF_FEC_FRSR = MCF_FEC_FRSR_R_FSTART(0x40);

    //     TFWR0[X_WMRK]   = 0 
    MCF_FEC_TFWR = 0;

    // Configure Ethernet hash table bits

    //     GAUR0[HASH_HIGH] = 0
    MCF_FEC_GAUR = 0;

    //     GALR0[HASH_LOW] = 0 
    MCF_FEC_GALR = 0;

    //     IAUR0[HASH_HIGH] = 0
    MCF_FEC_IAUR = 0;

    //     IALR0[HASH_LOW] = 0 
    MCF_FEC_IALR = 0;

    //     PALR0[ADDR_LOW] = 0 
    MCF_FEC_PALR = 0;

    //     PAUR0[ADDR_HIGH] = 0
    //     PAUR0[TYPE]     = $8808
    MCF_FEC_PAUR = MCF_FEC_PAUR_TYPE(0x8808);
}

/*********************************************************************
* init_flexcan - FlexCAN Module                                      *
**********************************************************************/
static void init_flexcan (void)
{
    // FlexCAN controller 0 disabled (CANMCR0[MDIS]=1)

    //     IMASK0[BUF15M]  = 0 
    //     IMASK0[BUF14M]  = 0 
    //     IMASK0[BUF13M]  = 0 
    //     IMASK0[BUF12M]  = 0 
    //     IMASK0[BUF11M]  = 0 
    //     IMASK0[BUF10M]  = 0 
    //     IMASK0[BUF9M]   = 0 
    //     IMASK0[BUF8M]   = 0 
    //     IMASK0[BUF7M]   = 0 
    //     IMASK0[BUF6M]   = 0 
    //     IMASK0[BUF5M]   = 0 
    //     IMASK0[BUF4M]   = 0 
    //     IMASK0[BUF3M]   = 0 
    //     IMASK0[BUF2M]   = 0 
    //     IMASK0[BUF1M]   = 0 
    //     IMASK0[BUF0M]   = 0 
    MCF_CAN_IMASK0 = 0;

    //     RXGMASK0[MI]    = $1fffffff
    MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI(0x1fffffff);

    //     RX14MASK0[MI]   = $1fffffff
    MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI(0x1fffffff);

    //     RX15MASK0[MI]   = $1fffffff
    MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI(0x1fffffff);

    //     CANCTRL0[PRESDIV] = 0
    //     CANCTRL0[RJW]   = 0 
    //     CANCTRL0[PSEG1] = 0 
    //     CANCTRL0[PSEG2] = 0 
    //     CANCTRL0[BOFFMSK] = 0
    //     CANCTRL0[ERRMSK] = 0
    //     CANCTRL0[CLK_SRC] = 0
    //     CANCTRL0[LPB]   = 0 
    //     CANCTRL0[SAMP]  = 0 
    //     CANCTRL0[BOFFREC] = 0
    //     CANCTRL0[TSYNC] = 0 
    //     CANCTRL0[LBUF]  = 0 
    //     CANCTRL0[LOM]   = 0 
    //     CANCTRL0[PROPSEG] = 0
    MCF_CAN_CANCTRL0 = 0;

    //     CANMCR0[MDIS]   = 1 
    //     CANMCR0[FRZ]    = 1 
    //     CANMCR0[HALT]   = 1 
    //     CANMCR0[SOFTRST] = 0
    //     CANMCR0[FRZACK] = 0 
    //     CANMCR0[SUPV]   = 1 
    //     CANMCR0[MAXMB]  = %1111
    MCF_CAN_CANMCR0 = MCF_CAN_CANMCR_MDIS       |
                      MCF_CAN_CANMCR_FRZ        |
                      MCF_CAN_CANMCR_HALT       |
                      MCF_CAN_CANMCR_SUPV       |
                      MCF_CAN_CANMCR_MAXMB(0xf);

    // FlexCAN controller 1 disabled (CANMCR1[MDIS]=1)

    //     IMASK1[BUF15M]  = 0 
    //     IMASK1[BUF14M]  = 0 
    //     IMASK1[BUF13M]  = 0 
    //     IMASK1[BUF12M]  = 0 
    //     IMASK1[BUF11M]  = 0 
    //     IMASK1[BUF10M]  = 0 
    //     IMASK1[BUF9M]   = 0 
    //     IMASK1[BUF8M]   = 0 
    //     IMASK1[BUF7M]   = 0 
    //     IMASK1[BUF6M]   = 0 
    //     IMASK1[BUF5M]   = 0 
    //     IMASK1[BUF4M]   = 0 
    //     IMASK1[BUF3M]   = 0 
    //     IMASK1[BUF2M]   = 0 
    //     IMASK1[BUF1M]   = 0 
    //     IMASK1[BUF0M]   = 0 
    MCF_CAN_IMASK1 = 0;

    //     RXGMASK1[MI]    = $1fffffff
    MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI(0x1fffffff);

    //     RX14MASK1[MI]   = $1fffffff
    MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI(0x1fffffff);

    //     RX15MASK1[MI]   = $1fffffff
    MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI(0x1fffffff);

    //     CANCTRL1[PRESDIV] = 0
    //     CANCTRL1[RJW]   = 0 
    //     CANCTRL1[PSEG1] = 0 
    //     CANCTRL1[PSEG2] = 0 
    //     CANCTRL1[BOFFMSK] = 0
    //     CANCTRL1[ERRMSK] = 0
    //     CANCTRL1[CLK_SRC] = 0
    //     CANCTRL1[LPB]   = 0 
    //     CANCTRL1[SAMP]  = 0 
    //     CANCTRL1[BOFFREC] = 0
    //     CANCTRL1[TSYNC] = 0 
    //     CANCTRL1[LBUF]  = 0 
    //     CANCTRL1[LOM]   = 0 
    //     CANCTRL1[PROPSEG] = 0
    MCF_CAN_CANCTRL1 = 0;

    //     CANMCR1[MDIS]   = 1 
    //     CANMCR1[FRZ]    = 1 
    //     CANMCR1[HALT]   = 1 
    //     CANMCR1[SOFTRST] = 0
    //     CANMCR1[FRZACK] = 0 
    //     CANMCR1[SUPV]   = 1 
    //     CANMCR1[MAXMB]  = %1111
    MCF_CAN_CANMCR1 = MCF_CAN_CANMCR_MDIS       |
                      MCF_CAN_CANMCR_FRZ        |
                      MCF_CAN_CANMCR_HALT       |
                      MCF_CAN_CANMCR_SUPV       |
                      MCF_CAN_CANMCR_MAXMB(0xf);
}

/*********************************************************************
* init_sram - On-chip SRAM                                           *
**********************************************************************/
static void init_sram (void)
{
    // Internal SRAM module enabled, address = $20000000
    // DMA/FEC access to SRAM block disabled
    // All access types except CPU space/interrupt acknowledge cycle allowed

    //     RAMBAR[BA]      = $2000
    //     RAMBAR[PRI1]    = 0 
    //     RAMBAR[PRI2]    = 0 
    //     RAMBAR[SPV]     = 0 
    //     RAMBAR[WP]      = 0 
    //     RAMBAR[C/I]     = 1 
    //     RAMBAR[SC]      = 0 
    //     RAMBAR[SD]      = 0 
    //     RAMBAR[UC]      = 0 
    //     RAMBAR[UD]      = 0 
    //     RAMBAR[V]       = 1 
    asm("move.l   #0x20000021,%d0");
    asm("movec    %d0,%RAMBAR0");
}

/*********************************************************************
* init_power_management - Power Management                           *
**********************************************************************/
static void init_power_management (void)
{
    // On executing STOP instruction, processor enters RUN mode
    // Mode is exited when an interrupt of level 1 or higher is received

    //     LPICR[ENBSTOP]  = 1 
    //     LPICR[XLPM_IPL] = 0 
    MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;

    //     LPCR[LPMD]      = 0 
    MCF_CCM_LPCR = 0;
}

/*********************************************************************
* init_qspi - Queued Serial Peripheral Interface (QSPI)              *
**********************************************************************/
static void init_qspi (void)
{
    // The QSPI_CLK clock is active high
    // Baud rate = 18.75 MBits per second
    // Bits per transfer = 16 (where enabled for command)
    // Wraparound mode disabled
    // QSPI_CS chip selects are active high
    // QSPI_Dout is actively driven between transfers
    // Transfer complete interrupt disabled

    //     QMR[MSTR]       = 1 
    //     QMR[DOHIE]      = 0 
    //     QMR[BITS]       = 0 
    //     QMR[CPOL]       = 0 
    //     QMR[CPHA]       = 1 
    //     QMR[BAUD]       = $2
    MCF_QSPI_QMR = MCF_QSPI_QMR_MSTR      |
                   MCF_QSPI_QMR_CPHA      |
                   MCF_QSPI_QMR_BAUD(0x2);

    //     QDLYR[SPE]      = 0 
    //     QDLYR[QCD]      = $4
    //     QDLYR[DTL]      = $4
    MCF_QSPI_QDLYR = MCF_QSPI_QDLYR_QCD(0x4) |
                     MCF_QSPI_QDLYR_DTL(0x4);

    //     QWR[HALT]       = 0 
    //     QWR[WREN]       = 0 
    //     QWR[WRTO]       = 0 
    //     QWR[CSIV]       = 0 
    //     QWR[ENDQP]      = 0 
    //     QWR[NEWQP]      = 0 
    MCF_QSPI_QWR = 0;

    //     QIR[WCEFB]      = 1 
    //     QIR[ABRTB]      = 1 
    //     QIR[ABRTL]      = 0 
    //     QIR[WCEFE]      = 0 
    //     QIR[ABRTE]      = 0 
    //     QIR[SPIFE]      = 0 
    //     QIR[WCEF]       = 0 
    //     QIR[ABRT]       = 0 
    //     QIR[SPIF]       = 0 
    MCF_QSPI_QIR = MCF_QSPI_QIR_WCEFB |
                   MCF_QSPI_QIR_ABRTB;
}

/*********************************************************************
* init_sdram_controller - SDRAM Controller                           *
**********************************************************************/
static void init_sdram_controller (void)
{
    // DRAM type is Synchronous (SDRAM)
    // SDRAM refresh timings:
    //     Number of clocks spent in refresh state = 3
    //     Refresh count = 70 (Refresh every 15.15 microseconds at 75.0 MHz bus clock)

    //     DCR[NAM]        = 0 
    //     DCR[COC]        = 0 
    //     DCR[IS]         = 1 
    //     DCR[RTIM]       = 0 
    //     DCR[RC]         = $46
    MCF_SDRAMC_DCR = MCF_SDRAMC_DCR_IS |
                     MCF_SDRAMC_DCR_RC(0x46);

    // Memory block 0: 16 MB of SDRAM at address $00000000
    // Port size: 32-bit port
    //  
    // Memory block 0 wired as follows:
    //    ColdFire Pin:    A15 A14 A13 A12 A11 A10 A9 A17 A19 A21     A22 A23
    //    SDRAM Pin:       A0  A1  A2  A3  A4  A5  A6 A7  A8  A9(CMD) BA0 BA1
    //  
    // Ensure that there is a delay of at least 100 microseconds from processor reset 
    // to the following code so that the SDRAM is ready for commands...

    // Memory block 0 Power-Up sequence:
    MCF_SDRAMC_DACR0 = 0x00001300;                // Initialise DACR0
    MCF_SDRAMC_DMR0 = 0x00fc0001;                 // Initialise DMR0

    // Memory block 0 Precharge sequence:
    MCF_SDRAMC_DACR0 = 0x00001308;                // Set DACR0[IP]
    * (vuint32 *) 0x00000000 = 0xcafebabe;        // Write to memory location to init. precharge

    // Memory block 0 Refresh sequence:
    MCF_SDRAMC_DACR0 = 0x00009300;                // Enable refresh bit in DACR0

	idle(1000);

    // Ensure a delay before the next step to allow SDRAM refresh to complete
    // (e.g. delay for 8 refresh cycles - see Manufacturers Data Sheet for delay period)

    // Memory block 0 Mode Register initialisation sequence:
    //     Burst length = 1
    //     Burst type = Sequential
    //     CAS Latency = 2 clocks
    //     Operating mode = Standard operation
    //     Write burst mode = Single location access
    MCF_SDRAMC_DACR0 = 0x00009340;                // Enable DACR0[IMRS]
    * (vuint32 *) 0x00000400 = 0xcafebabe;        // Initialise mode register to $020
    MCF_SDRAMC_DACR0 = 0x00009300;                // Disable DACR0[IMRS]

    // Memory block 1 not in use (DMR1[V] = 0)

    //     DMR1[BAM]       = 0 
    //     DMR1[WP]        = 0 
    //     DMR1[V]         = 0 
    MCF_SDRAMC_DMR1 = MCF_SDRAMC_DMR_BAM_256K;

    //     DACR1[BA]       = 0 
    //     DACR1[RE]       = 0 
    //     DACR1[CASL]     = 0 
    //     DACR1[CBM]      = 0 
    //     DACR1[IMRS]     = 0 
    //     DACR1[PS]       = 0 
    //     DACR1[IP]       = 0 
    MCF_SDRAMC_DACR1 = 0;
}

/*********************************************************************
* init_uarts - UART Module                                           *
**********************************************************************/
static void init_uarts (void)
{
    // Configure UART 0 (first UART channel)
    // Baud Rate = 19200
    // 8 data bits, 1 stop bit, No parity
    // /CTS input has no effect on the transmitter
    // /RTS output is not affected by receiver or transmitter

    // UART 0: Reset transmitter, receiver and mode register pointer

    //     UCR0[MISC]      = %011
    //     UCR0[TC]        = 0 
    //     UCR0[RC]        = 0 
    MCF_UART_UCR0 = MCF_UART_UCR_MISC(0x3);

    //     UCR0[MISC]      = %010
    //     UCR0[TC]        = 0 
    //     UCR0[RC]        = 0 
    MCF_UART_UCR0 = MCF_UART_UCR_MISC(0x2);

    //     UCR0[MISC]      = %001
    //     UCR0[TC]        = 0 
    //     UCR0[RC]        = 0 
    MCF_UART_UCR0 = MCF_UART_UCR_MISC(0x1);

    // UART 0 Mode Registers

    //     UMR10[RxRTS]    = 0 
    //     UMR10[RxIRQ/FFULL] = 0
    //     UMR10[ERR]      = 0 
    //     UMR10[PM]       = %10
    //     UMR10[PT]       = 0 
    //     UMR10[B/C]      = %11
    MCF_UART_UMR0 = MCF_UART_UMR_PM(0x2) |
                    MCF_UART_UMR_BC(0x3);

    //     UMR20[CM]       = 0 
    //     UMR20[TxRTS]    = 0 
    //     UMR20[TxCTS]    = 0 
    //     UMR20[SB]       = %0111
    MCF_UART_UMR0 = MCF_UART_UMR_SB(0x7);

    // UART 0 Clocking

    //     UCSR0[RCS]      = %1101
    //     UCSR0[TCS]      = %1101
    MCF_UART_UCSR0 = MCF_UART_UCSR_RCS(0xd) |
                     MCF_UART_UCSR_TCS(0xd);

    //     UDU0[MSB]       = 0 
    MCF_UART_UBG10 = 0;

    //     UDL0[LSB]       = $7a
    MCF_UART_UBG20 = 0x7a;

    // UART 0 Interrupt mask

    //     UIMR0[COS]      = 0 
    //     UIMR0[DB]       = 0 
    //     UIMR0[FFULL/RxRDY] = 0
    //     UIMR0[TxRDY]    = 0 
    MCF_UART_UIMR0 = 0;

    // UART 0 Miscellaneous

    //     UACR0[IEC]      = 0 
    MCF_UART_UACR0 = 0;

    // UART 0: Enable receiver and transmitter

    //     UCR0[MISC]      = 0 
    //     UCR0[TC]        = %01
    //     UCR0[RC]        = 0 
    MCF_UART_UCR0 = MCF_UART_UCR_TXC(0x1);

    //     UCR0[MISC]      = 0 
    //     UCR0[TC]        = 0 
    //     UCR0[RC]        = %01
    MCF_UART_UCR0 = MCF_UART_UCR_RXC(0x1);
}

/*********************************************************************
* init_dma_timers - DMA Timer Modules                                *
**********************************************************************/
static void init_dma_timers (void)
{
    // DMA Timer 0 disabled (DTMR0[RST] = 0)

    //     DTMR0[PS]       = 0 
    //     DTMR0[CE]       = 0 
    //     DTMR0[OM]       = 0 
    //     DTMR0[ORRI]     = 0 
    //     DTMR0[FRR]      = 0 
    //     DTMR0[CLK]      = 0 
    //     DTMR0[RST]      = 0 
    MCF_TIMER_DTMR0 = 0;

    //     DTXMR0[DMAEN]   = 0 
    //     DTXMR0[MODE16]  = 0 
    MCF_TIMER_DTXMR0 = 0;

    //     DTRR0[REF]      = $ffffffff
    MCF_TIMER_DTRR0 = 0xffffffff;

    // DMA Timer 1 disabled (DTMR1[RST] = 0)

    //     DTMR1[PS]       = 0 
    //     DTMR1[CE]       = 0 
    //     DTMR1[OM]       = 0 
    //     DTMR1[ORRI]     = 0 
    //     DTMR1[FRR]      = 0 
    //     DTMR1[CLK]      = 0 
    //     DTMR1[RST]      = 0 
    MCF_TIMER_DTMR1 = 0;

    //     DTXMR1[DMAEN]   = 0 
    //     DTXMR1[MODE16]  = 0 
    MCF_TIMER_DTXMR1 = 0;

    //     DTRR1[REF]      = $ffffffff
    MCF_TIMER_DTRR1 = 0xffffffff;

    // DMA Timer 2 disabled (DTMR2[RST] = 0)

    //     DTMR2[PS]       = 0 
    //     DTMR2[CE]       = 0 
    //     DTMR2[OM]       = 0 
    //     DTMR2[ORRI]     = 0 
    //     DTMR2[FRR]      = 0 
    //     DTMR2[CLK]      = 0 
    //     DTMR2[RST]      = 0 
    MCF_TIMER_DTMR2 = 0;

    //     DTXMR2[DMAEN]   = 0 
    //     DTXMR2[MODE16]  = 0 
    MCF_TIMER_DTXMR2 = 0;

    //     DTRR2[REF]      = $ffffffff
    MCF_TIMER_DTRR2 = 0xffffffff;

    // DMA Timer 3 disabled (DTMR3[RST] = 0)

    //     DTMR3[PS]       = 0 
    //     DTMR3[CE]       = 0 
    //     DTMR3[OM]       = 0 
    //     DTMR3[ORRI]     = 0 
    //     DTMR3[FRR]      = 0 
    //     DTMR3[CLK]      = 0 
    //     DTMR3[RST]      = 0 
    MCF_TIMER_DTMR3 = 0;

    //     DTXMR3[DMAEN]   = 0 
    //     DTXMR3[MODE16]  = 0 
    MCF_TIMER_DTXMR3 = 0;

    //     DTRR3[REF]      = $ffffffff
    MCF_TIMER_DTRR3 = 0xffffffff;
}

/**********************************************************************
* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules  *
***********************************************************************/
static void init_interrupt_timers (void)
{
    // PIT0 disabled (PCSR0[EN]=0)

    //     PCSR0[PRE]      = 0 
    //     PCSR0[DOZE]     = 0 
    //     PCSR0[DBG]      = 0 
    //     PCSR0[OVW]      = 0 
    //     PCSR0[PIE]      = 0 
    //     PCSR0[PIF]      = 0 
    //     PCSR0[RLD]      = 0 
    //     PCSR0[EN]       = 0 
    MCF_PIT_PCSR0 = 0;

    // PIT1 disabled (PCSR1[EN]=0)

    //     PCSR1[PRE]      = 0 
    //     PCSR1[DOZE]     = 0 
    //     PCSR1[DBG]      = 0 
    //     PCSR1[OVW]      = 0 
    //     PCSR1[PIE]      = 0 
    //     PCSR1[PIF]      = 0 
    //     PCSR1[RLD]      = 0 
    //     PCSR1[EN]       = 0 
    MCF_PIT_PCSR1 = 0;

    // PIT2 disabled (PCSR2[EN]=0)

    //     PCSR2[PRE]      = 0 
    //     PCSR2[DOZE]     = 0 
    //     PCSR2[DBG]      = 0 
    //     PCSR2[OVW]      = 0 
    //     PCSR2[PIE]      = 0 
    //     PCSR2[PIF]      = 0 
    //     PCSR2[RLD]      = 0 
    //     PCSR2[EN]       = 0 
    MCF_PIT_PCSR2 = 0;

    // PIT3 disabled (PCSR3[EN]=0)

    //     PCSR3[PRE]      = 0 
    //     PCSR3[DOZE]     = 0 
    //     PCSR3[DBG]      = 0 
    //     PCSR3[OVW]      = 0 
    //     PCSR3[PIE]      = 0 
    //     PCSR3[PIF]      = 0 
    //     PCSR3[RLD]      = 0 
    //     PCSR3[EN]       = 0 
    MCF_PIT_PCSR3 = 0;
}

/*********************************************************************
* init_watchdog_timers - Watchdog Timer Modules                      *
**********************************************************************/
static void init_watchdog_timers (void)
{
    // Watchdog Timer disabled (WCR[EN]=0)
    // NOTE: WCR and WMR cannot be written again until after the 
    // processor is reset.

    //     WCR[WAIT]       = 1 
    //     WCR[DOZE]       = 1 
    //     WCR[HALTED]     = 1 
    //     WCR[EN]         = 0 
    MCF_WTM_WCR = MCF_WTM_WCR_WAIT   |
                  MCF_WTM_WCR_DOZE   |
                  MCF_WTM_WCR_HALTED;

    //     WMR[WM]         = $ffff
    MCF_WTM_WMR = 0xffff;

    // Core Watchdog Timer disabled (CWCR[CWE]=0)

    //     CWCR[CWE]       = 0 
    //     CWCR[CWRI]      = 0 
    //     CWCR[CWT]       = 0 
    //     CWCR[CWTA]      = 0 
    //     CWCR[CWTAVAL]   = 0 
    //     CWCR[CWTIF]     = 0 
    MCF_SCM_CWCR = 0;
}

/*********************************************************************
* init_interrupt_controller - Interrupt Controller                   *
**********************************************************************/
static void init_interrupt_controller (void)
{
    // Configured interrupt sources in order of priority...
    // Level 7:  External interrupt /IRQ7, (initially masked)
    // Level 6:  External interrupt /IRQ6, (initially masked)
    // Level 5:  External interrupt /IRQ5, (initially masked)
    // Level 4:  External interrupt /IRQ4, (initially masked)
    // Level 3:  External interrupt /IRQ3, (initially masked)
    // Level 2:  External interrupt /IRQ2, (initially masked)
    // Level 1:  External interrupt /IRQ1, (initially masked)

    //     ICR001[IL]      = 0 
    //     ICR001[IP]      = 0 
    MCF_INTC0_ICR1 = 0;

    //     ICR002[IL]      = 0 
    //     ICR002[IP]      = 0 
    MCF_INTC0_ICR2 = 0;

    //     ICR003[IL]      = 0 
    //     ICR003[IP]      = 0 
    MCF_INTC0_ICR3 = 0;

    //     ICR004[IL]      = 0 
    //     ICR004[IP]      = 0 
    MCF_INTC0_ICR4 = 0;

    //     ICR005[IL]      = 0 
    //     ICR005[IP]      = 0 
    MCF_INTC0_ICR5 = 0;

    //     ICR006[IL]      = 0 
    //     ICR006[IP]      = 0 
    MCF_INTC0_ICR6 = 0;

    //     ICR007[IL]      = 0 
    //     ICR007[IP]      = 0 
    MCF_INTC0_ICR7 = 0;

    //     ICR008[IL]      = 0 
    //     ICR008[IP]      = 0 
    MCF_INTC0_ICR8 = 0;

    //     ICR009[IL]      = 0 
    //     ICR009[IP]      = 0 
    MCF_INTC0_ICR9 = 0;

    //     ICR010[IL]      = 0 
    //     ICR010[IP]      = 0 
    MCF_INTC0_ICR10 = 0;

    //     ICR011[IL]      = 0 
    //     ICR011[IP]      = 0 
    MCF_INTC0_ICR11 = 0;

    //     ICR012[IL]      = 0 
    //     ICR012[IP]      = 0 
    MCF_INTC0_ICR12 = 0;

    //     ICR013[IL]      = 0 
    //     ICR013[IP]      = 0 
    MCF_INTC0_ICR13 = 0;

    //     ICR014[IL]      = 0 
    //     ICR014[IP]      = 0 
    MCF_INTC0_ICR14 = 0;

    //     ICR015[IL]      = 0 
    //     ICR015[IP]      = 0 
    MCF_INTC0_ICR15 = 0;

    //     ICR017[IL]      = 0 
    //     ICR017[IP]      = 0 
    MCF_INTC0_ICR17 = 0;

    //     ICR018[IL]      = 0 
    //     ICR018[IP]      = 0 
    MCF_INTC0_ICR18 = 0;

    //     ICR019[IL]      = 0 
    //     ICR019[IP]      = 0 
    MCF_INTC0_ICR19 = 0;

    //     ICR020[IL]      = 0 
    //     ICR020[IP]      = 0 
    MCF_INTC0_ICR20 = 0;

    //     ICR021[IL]      = 0 
    //     ICR021[IP]      = 0 
    MCF_INTC0_ICR21 = 0;

    //     ICR022[IL]      = 0 
    //     ICR022[IP]      = 0 
    MCF_INTC0_ICR22 = 0;

    //     ICR023[IL]      = 0 
    //     ICR023[IP]      = 0 
    MCF_INTC0_ICR23 = 0;

    //     ICR024[IL]      = 0 
    //     ICR024[IP]      = 0 
    MCF_INTC0_ICR24 = 0;

    //     ICR025[IL]      = 0 
    //     ICR025[IP]      = 0 
    MCF_INTC0_ICR25 = 0;

    //     ICR026[IL]      = 0 
    //     ICR026[IP]      = 0 
    MCF_INTC0_ICR26 = 0;

    //     ICR027[IL]      = 0 
    //     ICR027[IP]      = 0 
    MCF_INTC0_ICR27 = 0;

    //     ICR028[IL]      = 0 
    //     ICR028[IP]      = 0 
    MCF_INTC0_ICR28 = 0;

    //     ICR029[IL]      = 0 
    //     ICR029[IP]      = 0 
    MCF_INTC0_ICR29 = 0;

    //     ICR030[IL]      = 0 
    //     ICR030[IP]      = 0 
    MCF_INTC0_ICR30 = 0;

    //     ICR031[IL]      = 0 
    //     ICR031[IP]      = 0 
    MCF_INTC0_ICR31 = 0;

    //     ICR032[IL]      = 0 
    //     ICR032[IP]      = 0 
    MCF_INTC0_ICR32 = 0;

    //     ICR033[IL]      = 0 
    //     ICR033[IP]      = 0 
    MCF_INTC0_ICR33 = 0;

    //     ICR034[IL]      = 0 
    //     ICR034[IP]      = 0 
    MCF_INTC0_ICR34 = 0;

    //     ICR035[IL]      = 0 
    //     ICR035[IP]      = 0 
    MCF_INTC0_ICR35 = 0;

    //     ICR036[IL]      = 0 
    //     ICR036[IP]      = 0 
    MCF_INTC0_ICR36 = 0;

    //     ICR037[IL]      = 0 
    //     ICR037[IP]      = 0 
    MCF_INTC0_ICR37 = 0;

    //     ICR038[IL]      = 0 
    //     ICR038[IP]      = 0 
    MCF_INTC0_ICR38 = 0;

    //     ICR039[IL]      = 0 
    //     ICR039[IP]      = 0 
    MCF_INTC0_ICR39 = 0;

    //     ICR040[IL]      = 0 
    //     ICR040[IP]      = 0 
    MCF_INTC0_ICR40 = 0;

    //     ICR041[IL]      = 0 
    //     ICR041[IP]      = 0 
    MCF_INTC0_ICR41 = 0;

    //     ICR042[IL]      = 0 
    //     ICR042[IP]      = 0 
    MCF_INTC0_ICR42 = 0;

    //     ICR043[IL]      = 0 
    //     ICR043[IP]      = 0 
    MCF_INTC0_ICR43 = 0;

    //     ICR044[IL]      = 0 
    //     ICR044[IP]      = 0 
    MCF_INTC0_ICR44 = 0;

    //     ICR045[IL]      = 0 
    //     ICR045[IP]      = 0 
    MCF_INTC0_ICR45 = 0;

    //     ICR046[IL]      = 0 
    //     ICR046[IP]      = 0 
    MCF_INTC0_ICR46 = 0;

    //     ICR047[IL]      = 0 
    //     ICR047[IP]      = 0 
    MCF_INTC0_ICR47 = 0;

    //     ICR048[IL]      = 0 
    //     ICR048[IP]      = 0 
    MCF_INTC0_ICR48 = 0;

    //     ICR049[IL]      = 0 
    //     ICR049[IP]      = 0 
    MCF_INTC0_ICR49 = 0;

    //     ICR050[IL]      = 0 
    //     ICR050[IP]      = 0 
    MCF_INTC0_ICR50 = 0;

    //     ICR051[IL]      = 0 
    //     ICR051[IP]      = 0 
    MCF_INTC0_ICR51 = 0;

    //     ICR052[IL]      = 0 
    //     ICR052[IP]      = 0 
    MCF_INTC0_ICR52 = 0;

    //     ICR053[IL]      = 0 
    //     ICR053[IP]      = 0 
    MCF_INTC0_ICR53 = 0;

    //     ICR054[IL]      = 0 
    //     ICR054[IP]      = 0 
    MCF_INTC0_ICR54 = 0;

    //     ICR055[IL]      = 0 
    //     ICR055[IP]      = 0 
    MCF_INTC0_ICR55 = 0;

    //     ICR056[IL]      = 0 
    //     ICR056[IP]      = 0 
    MCF_INTC0_ICR56 = 0;

    //     ICR057[IL]      = 0 
    //     ICR057[IP]      = 0 
    MCF_INTC0_ICR57 = 0;

    //     ICR058[IL]      = 0 
    //     ICR058[IP]      = 0 
    MCF_INTC0_ICR58 = 0;

    //     ICR059[IL]      = 0 
    //     ICR059[IP]      = 0 
    MCF_INTC0_ICR59 = 0;

    //     ICR060[IL]      = 0 
    //     ICR060[IP]      = 0 
    MCF_INTC0_ICR60 = 0;

    //     ICR108[IL]      = 0 
    //     ICR108[IP]      = 0 
    MCF_INTC1_ICR8 = 0;

    //     ICR109[IL]      = 0 
    //     ICR109[IP]      = 0 
    MCF_INTC1_ICR9 = 0;

    //     ICR110[IL]      = 0 
    //     ICR110[IP]      = 0 
    MCF_INTC1_ICR10 = 0;

    //     ICR111[IL]      = 0 
    //     ICR111[IP]      = 0 
    MCF_INTC1_ICR11 = 0;

    //     ICR112[IL]      = 0 
    //     ICR112[IP]      = 0 
    MCF_INTC1_ICR12 = 0;

    //     ICR113[IL]      = 0 
    //     ICR113[IP]      = 0 
    MCF_INTC1_ICR13 = 0;

    //     ICR114[IL]      = 0 
    //     ICR114[IP]      = 0 
    MCF_INTC1_ICR14 = 0;

    //     ICR115[IL]      = 0 
    //     ICR115[IP]      = 0 
    MCF_INTC1_ICR15 = 0;

    //     ICR116[IL]      = 0 
    //     ICR116[IP]      = 0 
    MCF_INTC1_ICR16 = 0;

    //     ICR117[IL]      = 0 
    //     ICR117[IP]      = 0 
    MCF_INTC1_ICR17 = 0;

    //     ICR118[IL]      = 0 
    //     ICR118[IP]      = 0 
    MCF_INTC1_ICR18 = 0;

    //     ICR119[IL]      = 0 
    //     ICR119[IP]      = 0 
    MCF_INTC1_ICR19 = 0;

    //     ICR120[IL]      = 0 
    //     ICR120[IP]      = 0 
    MCF_INTC1_ICR20 = 0;

    //     ICR121[IL]      = 0 
    //     ICR121[IP]      = 0 
    MCF_INTC1_ICR21 = 0;

    //     ICR122[IL]      = 0 
    //     ICR122[IP]      = 0 
    MCF_INTC1_ICR22 = 0;

    //     ICR123[IL]      = 0 
    //     ICR123[IP]      = 0 
    MCF_INTC1_ICR23 = 0;

    //     ICR124[IL]      = 0 
    //     ICR124[IP]      = 0 
    MCF_INTC1_ICR24 = 0;

    //     ICR125[IL]      = 0 
    //     ICR125[IP]      = 0 
    MCF_INTC1_ICR25 = 0;

    //     ICR127[IL]      = 0 
    //     ICR127[IP]      = 0 
    MCF_INTC1_ICR27 = 0;

    //     ICR128[IL]      = 0 
    //     ICR128[IP]      = 0 
    MCF_INTC1_ICR28 = 0;

    //     ICR129[IL]      = 0 
    //     ICR129[IP]      = 0 
    MCF_INTC1_ICR29 = 0;

    //     ICR130[IL]      = 0 
    //     ICR130[IP]      = 0 
    MCF_INTC1_ICR30 = 0;

    //     ICR131[IL]      = 0 
    //     ICR131[IP]      = 0 
    MCF_INTC1_ICR31 = 0;

    //     ICR132[IL]      = 0 
    //     ICR132[IP]      = 0 
    MCF_INTC1_ICR32 = 0;

    //     ICR133[IL]      = 0 
    //     ICR133[IP]      = 0 
    MCF_INTC1_ICR33 = 0;

    //     ICR134[IL]      = 0 
    //     ICR134[IP]      = 0 
    MCF_INTC1_ICR34 = 0;

    //     ICR135[IL]      = 0 
    //     ICR135[IP]      = 0 
    MCF_INTC1_ICR35 = 0;

    //     ICR136[IL]      = 0 
    //     ICR136[IP]      = 0 
    MCF_INTC1_ICR36 = 0;

    //     ICR137[IL]      = 0 
    //     ICR137[IP]      = 0 
    MCF_INTC1_ICR37 = 0;

    //     ICR138[IL]      = 0 
    //     ICR138[IP]      = 0 
    MCF_INTC1_ICR38 = 0;

    //     ICR139[IL]      = 0 
    //     ICR139[IP]      = 0 
    MCF_INTC1_ICR39 = 0;

    //     ICR140[IL]      = 0 
    //     ICR140[IP]      = 0 
    MCF_INTC1_ICR40 = 0;

    //     ICR141[IL]      = 0 
    //     ICR141[IP]      = 0 
    MCF_INTC1_ICR41 = 0;

    //     ICR142[IL]      = 0 
    //     ICR142[IP]      = 0 
    MCF_INTC1_ICR42 = 0;

    //     ICR159[IL]      = 0 
    //     ICR159[IP]      = 0 
    MCF_INTC1_ICR59 = 0;

    //     IMRH0[INT_MASK63] = 1
    //     IMRH0[INT_MASK62] = 1
    //     IMRH0[INT_MASK61] = 1
    //     IMRH0[INT_MASK60] = 1
    //     IMRH0[INT_MASK59] = 1
    //     IMRH0[INT_MASK58] = 1
    //     IMRH0[INT_MASK57] = 1
    //     IMRH0[INT_MASK56] = 1
    //     IMRH0[INT_MASK55] = 1
    //     IMRH0[INT_MASK54] = 1
    //     IMRH0[INT_MASK53] = 1
    //     IMRH0[INT_MASK52] = 1
    //     IMRH0[INT_MASK51] = 1
    //     IMRH0[INT_MASK50] = 1
    //     IMRH0[INT_MASK49] = 1
    //     IMRH0[INT_MASK48] = 1
    //     IMRH0[INT_MASK47] = 1
    //     IMRH0[INT_MASK46] = 1
    //     IMRH0[INT_MASK45] = 1
    //     IMRH0[INT_MASK44] = 1
    //     IMRH0[INT_MASK43] = 1
    //     IMRH0[INT_MASK42] = 1
    //     IMRH0[INT_MASK41] = 1
    //     IMRH0[INT_MASK40] = 1
    //     IMRH0[INT_MASK39] = 1
    //     IMRH0[INT_MASK38] = 1
    //     IMRH0[INT_MASK37] = 1
    //     IMRH0[INT_MASK36] = 1
    //     IMRH0[INT_MASK35] = 1
    //     IMRH0[INT_MASK34] = 1
    //     IMRH0[INT_MASK33] = 1
    //     IMRH0[INT_MASK32] = 1
    MCF_INTC0_IMRH = 0xffffffff;

    //     IMRL0[INT_MASK31] = 1
    //     IMRL0[INT_MASK30] = 1
    //     IMRL0[INT_MASK29] = 1
    //     IMRL0[INT_MASK28] = 1
    //     IMRL0[INT_MASK27] = 1
    //     IMRL0[INT_MASK26] = 1
    //     IMRL0[INT_MASK25] = 1
    //     IMRL0[INT_MASK24] = 1
    //     IMRL0[INT_MASK23] = 1
    //     IMRL0[INT_MASK22] = 1
    //     IMRL0[INT_MASK21] = 1
    //     IMRL0[INT_MASK20] = 1
    //     IMRL0[INT_MASK19] = 1
    //     IMRL0[INT_MASK18] = 1
    //     IMRL0[INT_MASK17] = 1
    //     IMRL0[INT_MASK16] = 1
    //     IMRL0[INT_MASK15] = 1
    //     IMRL0[INT_MASK14] = 1
    //     IMRL0[INT_MASK13] = 1
    //     IMRL0[INT_MASK12] = 1
    //     IMRL0[INT_MASK11] = 1
    //     IMRL0[INT_MASK10] = 1
    //     IMRL0[INT_MASK9] = 1
    //     IMRL0[INT_MASK8] = 1
    //     IMRL0[INT_MASK7] = 1
    //     IMRL0[INT_MASK6] = 1
    //     IMRL0[INT_MASK5] = 1
    //     IMRL0[INT_MASK4] = 1
    //     IMRL0[INT_MASK3] = 1
    //     IMRL0[INT_MASK2] = 1
    //     IMRL0[INT_MASK1] = 1
    //     IMRL0[INT_MASKALL] = 0
    MCF_INTC0_IMRL = 0xfffffffe;

    //     IMRH1[INT_MASK63] = 1
    //     IMRH1[INT_MASK62] = 1
    //     IMRH1[INT_MASK61] = 1
    //     IMRH1[INT_MASK60] = 1
    //     IMRH1[INT_MASK59] = 1
    //     IMRH1[INT_MASK58] = 1
    //     IMRH1[INT_MASK57] = 1
    //     IMRH1[INT_MASK56] = 1
    //     IMRH1[INT_MASK55] = 1
    //     IMRH1[INT_MASK54] = 1
    //     IMRH1[INT_MASK53] = 1
    //     IMRH1[INT_MASK52] = 1
    //     IMRH1[INT_MASK51] = 1
    //     IMRH1[INT_MASK50] = 1
    //     IMRH1[INT_MASK49] = 1
    //     IMRH1[INT_MASK48] = 1
    //     IMRH1[INT_MASK47] = 1
    //     IMRH1[INT_MASK46] = 1
    //     IMRH1[INT_MASK45] = 1
    //     IMRH1[INT_MASK44] = 1
    //     IMRH1[INT_MASK43] = 1
    //     IMRH1[INT_MASK42] = 1
    //     IMRH1[INT_MASK41] = 1
    //     IMRH1[INT_MASK40] = 1
    //     IMRH1[INT_MASK39] = 1
    //     IMRH1[INT_MASK38] = 1
    //     IMRH1[INT_MASK37] = 1
    //     IMRH1[INT_MASK36] = 1
    //     IMRH1[INT_MASK35] = 1
    //     IMRH1[INT_MASK34] = 1
    //     IMRH1[INT_MASK33] = 1
    //     IMRH1[INT_MASK32] = 1
    MCF_INTC1_IMRH = 0xffffffff;

    //     IMRL1[INT_MASK31] = 1
    //     IMRL1[INT_MASK30] = 1
    //     IMRL1[INT_MASK29] = 1
    //     IMRL1[INT_MASK28] = 1
    //     IMRL1[INT_MASK27] = 1
    //     IMRL1[INT_MASK26] = 1
    //     IMRL1[INT_MASK25] = 1
    //     IMRL1[INT_MASK24] = 1
    //     IMRL1[INT_MASK23] = 1
    //     IMRL1[INT_MASK22] = 1
    //     IMRL1[INT_MASK21] = 1
    //     IMRL1[INT_MASK20] = 1
    //     IMRL1[INT_MASK19] = 1
    //     IMRL1[INT_MASK18] = 1
    //     IMRL1[INT_MASK17] = 1
    //     IMRL1[INT_MASK16] = 1
    //     IMRL1[INT_MASK15] = 1
    //     IMRL1[INT_MASK14] = 1
    //     IMRL1[INT_MASK13] = 1
    //     IMRL1[INT_MASK12] = 1
    //     IMRL1[INT_MASK11] = 1
    //     IMRL1[INT_MASK10] = 1
    //     IMRL1[INT_MASK9] = 1
    //     IMRL1[INT_MASK8] = 1
    //     IMRL1[INT_MASK7] = 1
    //     IMRL1[INT_MASK6] = 1
    //     IMRL1[INT_MASK5] = 1
    //     IMRL1[INT_MASK4] = 1
    //     IMRL1[INT_MASK3] = 1
    //     IMRL1[INT_MASK2] = 1
    //     IMRL1[INT_MASK1] = 1
    //     IMRL1[INT_MASKALL] = 0
    MCF_INTC1_IMRL = 0xfffffffe;
}

/*********************************************************************
* init_pin_assignments - Pin Assignment and General Purpose I/O      *
**********************************************************************/
static void init_pin_assignments (void)
{
    // Pin assignments for port ADDR
    //     Pin A23        : A23 or CS6 (as configured at reset)
    //     Pin A22        : A22 or CS5 (as configured at reset)
    //     Pin A21        : A21 or CS4 (as configured at reset)

    //     PDDR_ADDR[DDADDR7] = 0
    //     PDDR_ADDR[DDADDR6] = 0
    //     PDDR_ADDR[DDADDR5] = 0
    MCF_GPIO_PDDR_APDDR = 0;

    //     PAR_AD[PAR_ADDR23] = 1
    //     PAR_AD[PAR_ADDR22] = 1
    //     PAR_AD[PAR_ADDR21] = 1
    //     PAR_AD[PAR_DATAL] = 1
    MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23 |
                      MCF_GPIO_PAR_AD_PAR_ADDR22 |
                      MCF_GPIO_PAR_AD_PAR_ADDR21 |
                      MCF_GPIO_PAR_AD_PAR_DATAL;

    // Pin assignments for ports DATAH and DATAL
    //     Pins are Data Bus D[15:0]

    //     PDDR_DATAH[DDDATAH7] = 0
    //     PDDR_DATAH[DDDATAH6] = 0
    //     PDDR_DATAH[DDDATAH5] = 0
    //     PDDR_DATAH[DDDATAH4] = 0
    //     PDDR_DATAH[DDDATAH3] = 0
    //     PDDR_DATAH[DDDATAH2] = 0
    //     PDDR_DATAH[DDDATAH1] = 0
    //     PDDR_DATAH[DDDATAH0] = 0
    MCF_GPIO_PDDR_DATAH = 0;

    //     PDDR_DATAL[DDDATAL7] = 0
    //     PDDR_DATAL[DDDATAL6] = 0
    //     PDDR_DATAL[DDDATAL5] = 0
    //     PDDR_DATAL[DDDATAL4] = 0
    //     PDDR_DATAL[DDDATAL3] = 0
    //     PDDR_DATAL[DDDATAL2] = 0
    //     PDDR_DATAL[DDDATAL1] = 0
    //     PDDR_DATAL[DDDATAL0] = 0
    MCF_GPIO_PDDR_DATAL = 0;

    // Pin assignments for port BUSCTL
    //     Pin /OE        : External bus output enable, /OE
    //     Pin /TA        : External bus transfer acknowledge, /TA
    //     Pin /TEA       : External bus transfer error acknowledge, /TEA
    //     Pin R/W        : External bus read/write indication, R/W
    //     Pin TSIZ1      : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
    //     Pin TSIZ0      : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
    //     Pin /TS        : External bus transfer start, /TS
    //     Pin /TIP       : External bus transfer in progess, /TIP

    //     PDDR_BUSCTL[DDBUSCTL7] = 0
    //     PDDR_BUSCTL[DDBUSCTL6] = 0
    //     PDDR_BUSCTL[DDBUSCTL5] = 0
    //     PDDR_BUSCTL[DDBUSCTL4] = 0
    //     PDDR_BUSCTL[DDBUSCTL3] = 0
    //     PDDR_BUSCTL[DDBUSCTL2] = 0
    //     PDDR_BUSCTL[DDBUSCTL1] = 0
    //     PDDR_BUSCTL[DDBUSCTL0] = 0
    MCF_GPIO_PDDR_BUSCTL = 0;

    //     PAR_BUSCTL[PAR_OE] = 1
    //     PAR_BUSCTL[PAR_TA] = 1
    //     PAR_BUSCTL[PAR_TEA] = %11
    //     PAR_BUSCTL[PAR_RWB] = 1
    //     PAR_BUSCTL[PAR_TSIZ1] = 1
    //     PAR_BUSCTL[PAR_TSIZ0] = 1
    //     PAR_BUSCTL[PAR_TS] = %11
    //     PAR_BUSCTL[PAR_TIP] = %11
    MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE       |
                          MCF_GPIO_PAR_BUSCTL_PAR_TA       |
                          MCF_GPIO_PAR_BUSCTL_PAR_TEA(0x3) |
                          MCF_GPIO_PAR_BUSCTL_PAR_RWB      |
                          MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1    |
                          MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0    |
                          MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3)  |
                          MCF_GPIO_PAR_BUSCTL_PAR_TIP(0x3);

    // Pin assignments for port BS
    //     Pin /BS3       : External byte strobe /BS3
    //     Pin /BS2       : External byte strobe /BS2
    //     Pin /BS1       : External byte strobe /BS1
    //     Pin /BS0       : External byte strobe /BS0

    //     PDDR_BS[DDBS3]  = 0 
    //     PDDR_BS[DDBS2]  = 0 
    //     PDDR_BS[DDBS1]  = 0 
    //     PDDR_BS[DDBS0]  = 0 
    MCF_GPIO_PDDR_BS = 0;

    //     PAR_BS[PAR_BS3] = 1 
    //     PAR_BS[PAR_BS2] = 1 
    //     PAR_BS[PAR_BS1] = 1 
    //     PAR_BS[PAR_BS0] = 1 
    MCF_GPIO_PAR_BS = MCF_GPIO_PAR_BS_PAR_BS3 |
                      MCF_GPIO_PAR_BS_PAR_BS2 |
                      MCF_GPIO_PAR_BS_PAR_BS1 |
                      MCF_GPIO_PAR_BS_PAR_BS0;

    // Pin assignments for port CS
    //     Pin /CS7       : GPIO input
    //     Pin /CS6       : GPIO input
    //     Pin /CS5       : GPIO input
    //     Pin /CS4       : GPIO input
    //     Pin /CS3       : SDRAM chip select /SD_CS1
    //     Pin /CS2       : SDRAM chip select /SD_CS0
    //     Pin /CS1       : GPIO input

    //     PDDR_CS[DDCS7]  = 0 
    //     PDDR_CS[DDCS6]  = 0 
    //     PDDR_CS[DDCS5]  = 0 
    //     PDDR_CS[DDCS4]  = 0 
    //     PDDR_CS[DDCS3]  = 0 
    //     PDDR_CS[DDCS2]  = 0 
    //     PDDR_CS[DDCS1]  = 0 
    MCF_GPIO_PDDR_CS = 0;

    //     PAR_CS[PAR_CS7] = 0 
    //     PAR_CS[PAR_CS6] = 0 
    //     PAR_CS[PAR_CS5] = 0 
    //     PAR_CS[PAR_CS4] = 0 
    //     PAR_CS[PAR_CS3] = 1 
    //     PAR_CS[PAR_CS2] = 1 
    //     PAR_CS[PAR_CS1] = 0 
    MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS3 |
                      MCF_GPIO_PAR_CS_PAR_CS2;

    // Pin assignments for port SDRAM
    //     Pin /SD_WE     : SDRAM controller /SD_WE
    //     Pin /SD_SCAS   : SDRAM controller /SD_SCAS
    //     Pin /SD_SRAS   : SDRAM controller /SD_SRAS
    //     Pin /SD_SCKE   : SDRAM controller /SD_SCKE
    //     Pin /SD_CS1    : SDRAM controller /SD_CS1
    //     Pin /SD_CS0    : SDRAM controller /SD_CS0

    //     PDDR_SDRAM[DDSDRAM5] = 0
    //     PDDR_SDRAM[DDSDRAM4] = 0
    //     PDDR_SDRAM[DDSDRAM3] = 0
    //     PDDR_SDRAM[DDSDRAM2] = 0
    //     PDDR_SDRAM[DDSDRAM1] = 0
    //     PDDR_SDRAM[DDSDRAM0] = 0
    MCF_GPIO_PDDR_SDRAM = 0;

    //     PAR_SDRAM[PAR_CSSDCS3] = 1
    //     PAR_SDRAM[PAR_CSSDCS2] = 1
    //     PAR_SDRAM[PAR_SDWE] = 1
    //     PAR_SDRAM[PAR_SCAS] = 1
    //     PAR_SDRAM[PAR_SRAS] = 1
    //     PAR_SDRAM[PAR_SCKE] = 1
    //     PAR_SDRAM[PAR_SDCS1] = 1
    //     PAR_SDRAM[PAR_SDCS0] = 1
    MCF_GPIO_PAR_SDRAM = (0x1 << 7)                   |
                         (0x1 << 6)                   |
                         MCF_GPIO_PAR_SDRAM_PAR_SDWE  |
                         MCF_GPIO_PAR_SDRAM_PAR_SCAS  |
                         MCF_GPIO_PAR_SDRAM_PAR_SRAS  |
                         MCF_GPIO_PAR_SDRAM_PAR_SCKE  |
                         MCF_GPIO_PAR_SDRAM_PAR_SDCS1 |
                         MCF_GPIO_PAR_SDRAM_PAR_SDCS0;

    // Pin assignments for port FECI2C
    //     Pin EMDC       : Ethernet management data clock, EMDC
    //     Pin EMDIO      : Ethernet management data, EMDIO
    //     Pin SCL        : I2C serial clock, SCL
    //     Pin SDA        : I2C serial data, SDA

    //     PDDR_FECI2C[DDFECI2C3] = 0
    //     PDDR_FECI2C[DDFECI2C2] = 0
    //     PDDR_FECI2C[DDFECI2C1] = 0
    //     PDDR_FECI2C[DDFECI2C0] = 0
    MCF_GPIO_PDDR_FECI2C = 0;

    //     PAR_FECI2C[PAR_EMDC] = %11
    //     PAR_FECI2C[PAR_EMDIO] = %11
    //     PAR_FECI2C[PAR_SCL] = %11
    //     PAR_FECI2C[PAR_SDA] = %11
    MCF_GPIO_PAR_FECI2C = MCF_GPIO_PAR_FECI2C_PAR_EMDC(0x3)  |
                          MCF_GPIO_PAR_FECI2C_PAR_EMDIO(0x3) |
                          MCF_GPIO_PAR_FECI2C_PAR_SCL(0x3)   |
                          MCF_GPIO_PAR_FECI2C_PAR_SDA(0x3);

    // Pin assignments for port UARTL
    //     Pin U1RXD      : GPIO input
    //     Pin U1TXD      : GPIO input
    //     Pin /U1CTS     : GPIO input
    //     Pin /U1RTS     : GPIO input
    //     Pin U0RXD      : UART 0 receive data, U0RXD
    //     Pin U0TXD      : UART 0 transmit data, U0TXD
    //     Pin /U0CTS     : UART 0 clear-to-send, /U0CTS
    //     Pin /U0RTS     : UART 0 request-to-send, /U0RTS

    //     PDDR_UARTL[DDUARTL7] = 0
    //     PDDR_UARTL[DDUARTL6] = 0
    //     PDDR_UARTL[DDUARTL5] = 0
    //     PDDR_UARTL[DDUARTL4] = 0
    //     PDDR_UARTL[DDUARTL3] = 0
    //     PDDR_UARTL[DDUARTL2] = 0
    //     PDDR_UARTL[DDUARTL1] = 0
    //     PDDR_UARTL[DDUARTL0] = 0
    MCF_GPIO_PDDR_UARTL = 0;

    //     PAR_UART[PAR_DREQ2] = 0
    //     PAR_UART[PAR_CAN1EN] = 0
    //     PAR_UART[PAR_U2RXD] = 0
    //     PAR_UART[PAR_U2TXD] = 0
    //     PAR_UART[PAR_U1RXD] = 0
    //     PAR_UART[PAR_U1TXD] = 0
    //     PAR_UART[PAR_U1CTS] = 0
    //     PAR_UART[PAR_U1RTS] = 0
    //     PAR_UART[PAR_U0RXD] = 1
    //     PAR_UART[PAR_U0TXD] = 1
    //     PAR_UART[PAR_U0CTS] = 1
    //     PAR_UART[PAR_U0RTS] = 1
    MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD |
                        MCF_GPIO_PAR_UART_PAR_U0TXD |
                        MCF_GPIO_PAR_UART_PAR_U0CTS |
                        MCF_GPIO_PAR_UART_PAR_U0RTS;

    // Pin assignments for port UARTH
    //     Pin U2TXD      : GPIO input
    //     Pin U2RXD      : GPIO input
    //     Pin /IRQ2      : Interrupt request /IRQ2 or GPIO

    //     PDDR_UARTH[DDUARTH1] = 0
    //     PDDR_UARTH[DDUARTH0] = 0
    MCF_GPIO_PDDR_UARTH = 0;

    // Pin assignments for port QSPI
    //     Pin QSPI_PCS1  : QSPI peripheral chip select QSPI_PCS1
    //     Pin QSPI_PCS0  : QSPI peripheral chip select QSPI_PCS0
    //     Pin QSPI_DIN   : QSPI serial input data, QSPI_DIN
    //     Pin QSPI_DOUT  : QSPI serial output data, QSPI_DOUT
    //     Pin QSPI_SCK   : QSPI serial clock, QSPI_SCK

    //     PDDR_QSPI[DDQSPI4] = 0
    //     PDDR_QSPI[DDQSPI3] = 0
    //     PDDR_QSPI[DDQSPI2] = 0
    //     PDDR_QSPI[DDQSPI1] = 0
    //     PDDR_QSPI[DDQSPI0] = 0
    MCF_GPIO_PDDR_QSPI = 0;

    //     PAR_QSPI[PAR_PCS1] = %11
    //     PAR_QSPI[PAR_PCS0] = 1
    //     PAR_QSPI[PAR_DIN] = %11
    //     PAR_QSPI[PAR_DOUT] = 1
    //     PAR_QSPI[PAR_SCK] = %11
    MCF_GPIO_PAR_QSPI = MCF_GPIO_PAR_QSPI_PAR_PCS1(0x3) |
                        MCF_GPIO_PAR_QSPI_PAR_PCS0      |
                        MCF_GPIO_PAR_QSPI_PAR_DIN(0x3)  |
                        MCF_GPIO_PAR_QSPI_PAR_DOUT      |
                        MCF_GPIO_PAR_QSPI_PAR_SCK(0x3);

    // Pin assignments for port TIMER
    //     Pin T3IN       : QSPI peripheral chip select QSPI_PCS2
    //     Pin T2IN       : DMA request /DREQ2
    //     Pin T1IN       : DMA request /DREQ1
    //     Pin T0IN       : DMA request /DREQ0
    //     Pin T3OUT      : QSPI peripheral chip select QSPI_PCS3
    //     Pin T2OUT      : DMA acknowledge /DACK2
    //     Pin T1OUT      : DMA acknowledge /DACK1
    //     Pin T0OUT      : DMA acknowledge /DACK0

    //     PDDR_TIMER[DDTIMER7] = 0
    //     PDDR_TIMER[DDTIMER6] = 0
    //     PDDR_TIMER[DDTIMER5] = 0
    //     PDDR_TIMER[DDTIMER4] = 0
    //     PDDR_TIMER[DDTIMER3] = 0
    //     PDDR_TIMER[DDTIMER2] = 0
    //     PDDR_TIMER[DDTIMER1] = 0
    //     PDDR_TIMER[DDTIMER0] = 0
    MCF_GPIO_PDDR_TIMER = 0;

    //     PAR_TIMER[PAR_T3IN] = %01
    //     PAR_TIMER[PAR_T2IN] = %10
    //     PAR_TIMER[PAR_T1IN] = %10
    //     PAR_TIMER[PAR_T0IN] = %10
    //     PAR_TIMER[PAR_T3OUT] = %01
    //     PAR_TIMER[PAR_T2OUT] = %10
    //     PAR_TIMER[PAR_T1OUT] = %10
    //     PAR_TIMER[PAR_T0OUT] = %10
    MCF_GPIO_PAR_TIMER = MCF_GPIO_PAR_TIMER_PAR_T3IN(0x1)  |
                         MCF_GPIO_PAR_TIMER_PAR_T2IN(0x2)  |
                         MCF_GPIO_PAR_TIMER_PAR_T1IN(0x2)  |
                         MCF_GPIO_PAR_TIMER_PAR_T0IN(0x2)  |
                         MCF_GPIO_PAR_TIMER_PAR_T3OUT(0x1) |
                         MCF_GPIO_PAR_TIMER_PAR_T2OUT(0x2) |
                         MCF_GPIO_PAR_TIMER_PAR_T1OUT(0x2) |
                         MCF_GPIO_PAR_TIMER_PAR_T0OUT(0x2);

    // Pin assignments for port ETPU
    //     Pin TRCLK      : eTPU external TCR clock, TCRCLK
    //     Pin UTPU_ODIS  : GPIO input
    //     Pin ETPU_ODIS  : eTPU lower channel output disable, LTPU_ODIS

    //     PDDR_ETPU[DDETPU2] = 0
    //     PDDR_ETPU[DDETPU1] = 0
    //     PDDR_ETPU[DDETPU0] = 0
    MCF_GPIO_PDDR_ETPU = 0;

    //     PAR_ETPU[PAR_TCRCLK] = 1
    //     PAR_ETPU[PAR_UTPU_ODIS] = 0
    //     PAR_ETPU[PAR_LTPU_ODIS] = 1
    MCF_GPIO_PAR_ETPU = MCF_GPIO_PAR_ETPU_PAR_TCRCLK |
                        MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS;
}