#
# Processor initialization file for MCF5235
# for use with gdb.
#
# Written by Csaba Kormendy <csaba.kormendy@quadros.com>
#


#################################
# This first section defines a  #
# number of commands to be used #
# near the end/bottom of this   #
# script file.                  #
#################################


#################################

define delay_a

set $dela = 0

while ($dela < 10000)
  set $dela += 1
end

end

#################################

define delay_b

set $delb = 0

while ($delb < 20000)
  set $delb += 1
end

end

#################################

define delay_c

set $delc = 0

while ($delc < 30000)
  set $delc += 1
end

end

#################################

define mcf523xevb_init

#
# Set VBR to the beginning of what will be SDRAM
# VBR is an absolute CPU register
# SDRAM is at 0x00000000+0x0400000
#
set $vbr = 0x20000000

#
# Set RAMBAR = 0x20000001
# RAMBAR is an absolute CPU register
# This is the location of the internal 64k of SRAM on the chip
#
set $rambar = 0x20000001

#
# Set PAR_SDRAM to allow SDRAM signals to be enabled
#
set *(unsigned char *)0x40100046 = 0x3F

#
# Set PAR_AD to allow 32-bit SDRAM if the exteranl boot device is 16-bits
#
set *(unsigned char *)0x40100040 = 0xE1

#
# 1MB ASRAM on CS1 at 0x30000000
#
#  CSAR1, CSMR1, CSCR1
#
set *(unsigned short *)0x4000008C =     0x3000
set *(unsigned long  *)0x40000090 = 0x000F0001
set *(unsigned short *)0x40000096 =     0x3D20

#
# 2MB FLASH on CS0 at 0xFFE00000
#
#  CSAR0, CSMR0, CSCR0
#
set *(unsigned short *)0x40000080 =     0xFFE0
set *(unsigned long  *)0x40000084 = 0x001F0001
set *(unsigned short *)0x4000008A =     0x1980

delay_a

#
# SDRAM
# Like the 5307 and 5407 Cadre 3 boards, this board uses DCR,DACR, DMR to access SDRAM
#
#  DCR, DACR0, DMR0
#
set *(unsigned short *)0x40000040 =     0x0446
set *(unsigned long  *)0x40000048 = 0x00002300
set *(unsigned long  *)0x4000004C = 0x00FC0001

#
# DACR0, write data to 0x0000_0000
#
set *(unsigned long  *)0x40000048 = 0x00002308
set *(unsigned long  *)0x00000000 = 0x00000000

delay_b

#
# DACR0, DACR0
#
set *(unsigned long  *)0x40000048 = 0x0000A308
set *(unsigned long  *)0x40000048 = 0x0000A348

set *(unsigned long  *)0x00000400 = 0x00000000

delay_c

set *(unsigned long  *)0x00000400 = 0x00000000

delay_c

#
# Disable the watchdog timer in WCR
#
set *(unsigned short *)0x40140000 = 0x0000

end

#################################

#
# MCF523x Reference Manual p 11-3
#
# IPSBAR defaults to 0x4000_0000
#

define leds_init

# Set DTOUT0,1,2,3 to act as GPIO
set *(unsigned short *)(0x40000000 + 0x10004C) = 0x0000

# Set Data Direction of DTOUT0,1,2,3 to Output
set *(unsigned char *)(0x40000000 + 0x10001B) = 0xFF

end

##########

define leds_on

# Write 0 to turn LEDs on
set *(unsigned char *)(0x40000000 + 0x10000B) = 0x00

end

##########

define leds_off

# Write 1 to turn LEDs off
set *(unsigned char *)(0x40000000 + 0x10000B) = 0xFF

end

##########

define leds_flash1

leds_on

delay_a

leds_off

delay_a

end

##########

define leds_flash

leds_init

set $loops = 0

while ($loops < 5)
  set $loops += 1
  leds_flash1
end

end

#################################


#################################
# Use the commands that have    #
# been defined in order to      #
# initialize the target         #
# hardware.                     #
#################################


#
# Connect to the target.
#
#                                    (typically)
#  /dev/bdmcf0 --> I/O port: 0x0378 --> LPT1
#  /dev/bdmcf1 --> I/O port: 0x0278 --> LPT2
#  /dev/bdmcf2 --> I/O port: 0x03BC --> LPT3
#  /dev/bdmcf3 --> I/O port: 0x02BC --> LPT4
#
# Uncomment one of the following lines as
# appropriate for your configuration.
#
target bdm /dev/bdmcf0
#target bdm /dev/bdmcf1
#target bdm /dev/bdmcf2
#target bdm /dev/bdmcf3

mcf523xevb_init

#leds_flash