#
# from http://mailman.uclinux.org/pipermail/uclinux-dev/2003-September/021123.html
# written by Phil Wilshire <philwil@earthlink.net>
#     http://www.sysdcs.com
#

#
# Connect to the target.
#
#                                    (typically)
#  /dev/bdmcf0 --> I/O port: 0x0378 --> LPT1
#  /dev/bdmcf1 --> I/O port: 0x0278 --> LPT2
#  /dev/bdmcf2 --> I/O port: 0x03BC --> LPT3
#  /dev/bdmcf3 --> I/O port: 0x02BC --> LPT4
#
# Uncomment one of the following lines as
# appropriate for your configuration.
#
target bdm /dev/bdmcf0
#target bdm /dev/bdmcf1
#target bdm /dev/bdmcf2
#target bdm /dev/bdmcf3

if 0
x 0x00000000
x
x
end

define addresses

set $myipsbar = 0x40000001
set $myrambar = $myipsbar -1 + 0x008    


# Pll
set $myclocksyncr = $myipsbar -1 + 0x120000    
set $myclocksynsr = $myipsbar -1 + 0x120002    

# Uart
set $mygpio_puapar = $myipsbar -1 + 0x10005C    

# CS0-6
set $myuart0_umr   = $myipsbar -1 + 0x200    
set $myuart0_ucsr  = $myipsbar -1 + 0x204    
set $myuart0_ucr   = $myipsbar -1 + 0x208    
set $myuart0_utb   = $myipsbar -1 + 0x20c    
set $myuart0_urb   = $myipsbar -1 + 0x20c    
set $myuart0_uimr  = $myipsbar -1 + 0x214    
set $myuart0_ubg1  = $myipsbar -1 + 0x218    
set $myuart0_ubg2  = $myipsbar -1 + 0x21c    

set $mycs0_csar   = $myipsbar -1 + 0x80    
set $mycs0_csmr   = $myipsbar -1 + 0x84    
set $mycs0_cscr   = $myipsbar -1 + 0x8A    

set $mycs1_csar   = $myipsbar -1 + 0x8C    
set $mycs1_csmr   = $myipsbar -1 + 0x90    
set $mycs1_cscr   = $myipsbar -1 + 0x96    

set $mycs2_csar   = $myipsbar -1 + 0x98    
set $mycs2_csmr   = $myipsbar -1 + 0x9C    
set $mycs2_cscr   = $myipsbar -1 + 0xA2    

set $mycs3_csar   = $myipsbar -1 + 0xA4    
set $mycs3_csmr   = $myipsbar -1 + 0xA8    
set $mycs3_cscr   = $myipsbar -1 + 0xAE    

set $mycs4_csar   = $myipsbar -1 + 0xB0    
set $mycs4_csmr   = $myipsbar -1 + 0xB4    
set $mycs4_cscr   = $myipsbar -1 + 0xBA    

set $mycs5_csar   = $myipsbar -1 + 0xBC    
set $mycs5_csmr   = $myipsbar -1 + 0xC0    
set $mycs5_cscr   = $myipsbar -1 + 0xC6    

set $mycs6_csar   = $myipsbar -1 + 0xC8    
set $mycs6_csmr   = $myipsbar -1 + 0xCC    
set $mycs6_cscr   = $myipsbar -1 + 0xD2   


#sdram
set $mysdramc_dcr     = $myipsbar -1 + 0x40    
set $mysdramc_dacr0   = $myipsbar -1 + 0x48
set $mysdramc_dmr0    = $myipsbar -1 + 0x4C
set $mysdramc_dacr1   = $myipsbar -1 + 0x50
set $mysdramc_dmr1    = $myipsbar -1 + 0x54

# GPIO
set $mypbcdpar = $myipsbar -1 + 0x100050    
set $mypjpar  = $myipsbar -1 + 0x100054 
set $mypuapar  = $myipsbar -1 + 0x10005C   

#CAN

set $mycanmcr     = $myipsbar -1 + 0x1C0000   
set $mycanctrl0   = $myipsbar -1 + 0x1C0006   
set $mycanctrl1   = $myipsbar -1 + 0x1C0007   
set $mycanpresdiv = $myipsbar -1 + 0x1C0008
set $mycanctrl2   = $myipsbar -1 + 0x1C0009   

set $mycanmb0ctrl = $myipsbar -1 + 0x1C0080
set $mycanmb0idh  = $myipsbar -1 + 0x1C0082
set $mycanmb0idl  = $myipsbar -1 + 0x1C0084

set $mycanmb1ctrl = $myipsbar -1 + 0x1C0090
set $mycanmb1idh  = $myipsbar -1 + 0x1C0092
set $mycanmb1idl  = $myipsbar -1 + 0x1C0094
   
set $mycanmb2ctrl = $myipsbar -1 + 0x1C00A0
set $mycanmb2idh  = $myipsbar -1 + 0x1C00A2
set $mycanmb2idl  = $myipsbar -1 + 0x1C00A4
   
set $mycanmb3ctrl = $myipsbar -1 + 0x1C00B0
set $mycanmb3idh  = $myipsbar -1 + 0x1C00B2
set $mycanmb3idl  = $myipsbar -1 + 0x1C00B4
   
set $mycanmb4ctrl = $myipsbar -1 + 0x1C00C0
set $mycanmb4idh  = $myipsbar -1 + 0x1C00C2
set $mycanmb4idl  = $myipsbar -1 + 0x1C00C4
   
set $mycanmb5ctrl = $myipsbar -1 + 0x1C00D0
set $mycanmb5idh  = $myipsbar -1 + 0x1C00D2
set $mycanmb5idl  = $myipsbar -1 + 0x1C00D4
   
set $mycanmb6ctrl = $myipsbar -1 + 0x1C00E0
set $mycanmb6idh  = $myipsbar -1 + 0x1C00E2
set $mycanmb6idl  = $myipsbar -1 + 0x1C00E4
   
set $mycanmb7ctrl = $myipsbar -1 + 0x1C00F0
set $mycanmb7idh  = $myipsbar -1 + 0x1C00F2
set $mycanmb7idl  = $myipsbar -1 + 0x1C00F4
   
set $mycanmb8ctrl = $myipsbar -1 + 0x1C0100
set $mycanmb8idh  = $myipsbar -1 + 0x1C0102
set $mycanmb8idl  = $myipsbar -1 + 0x1C0104
   
set $mycanmb9ctrl = $myipsbar -1 + 0x1C0110
set $mycanmb9idh  = $myipsbar -1 + 0x1C0112
set $mycanmb9idl  = $myipsbar -1 + 0x1C0114

set $mycanmb10ctrl = $myipsbar -1 + 0x1C0120
set $mycanmb10idh  = $myipsbar -1 + 0x1C0122
set $mycanmb10idl  = $myipsbar -1 + 0x1C0124

set $mycanmb11ctrl = $myipsbar -1 + 0x1C0130
set $mycanmb11idh  = $myipsbar -1 + 0x1C0132
set $mycanmb11idl  = $myipsbar -1 + 0x1C0134
   
set $mycanmb12ctrl = $myipsbar -1 + 0x1C0140
set $mycanmb12idh  = $myipsbar -1 + 0x1C0142
set $mycanmb12idl  = $myipsbar -1 + 0x1C0144

set $mycanmb13ctrl = $myipsbar -1 + 0x1C0150
set $mycanmb13idh  = $myipsbar -1 + 0x1C0152
set $mycanmb13idl  = $myipsbar -1 + 0x1C0154

set $mycanmb14ctrl = $myipsbar -1 + 0x1C0160
set $mycanmb14idh  = $myipsbar -1 + 0x1C0162
set $mycanmb14idl  = $myipsbar -1 + 0x1C0164

set $mycanmb15ctrl = $myipsbar -1 + 0x1C0170
set $mycanmb15idh  = $myipsbar -1 + 0x1C0172
set $mycanmb15idl  = $myipsbar -1 + 0x1C0174

set $mycanrxgmask  = $myipsbar -1 + 0x1C0010


# arrow system latch

set $arrow_latch  = 0x3200f000

# setup for SDRAM access
#( ((!FPGA_SDRAM_NOT_5382_ACCESS)  0x1000
# & (! SDRAM_BUS_DIR_IN))          0x0800
#  | RUN_MODE_BASE_MASK ); 





# end addresses
end


define setup_can

# FRZ 0x4000 HALT 0x1000 SELFWAKE  0x40
set *(unsigned short *)$mycanmcr = 0x5040

#RXMODE =0x04
set *(unsigned char *)$mycanctrl0 = 0x04

#LOM 0x08
set *(unsigned char *)$mycanctrl1 = 0x08

set *(unsigned char *)$mycanpresdiv = 0x83

set *(unsigned short *)$mycanmb0ctrl = 0x0088
set *(unsigned short *)$mycanmb1ctrl = 0x0000
set *(unsigned short *)$mycanmb2ctrl = 0x0088
set *(unsigned short *)$mycanmb3ctrl = 0x0088
set *(unsigned short *)$mycanmb4ctrl = 0x0088
set *(unsigned short *)$mycanmb5ctrl = 0x0088
set *(unsigned short *)$mycanmb6ctrl = 0x0088
set *(unsigned short *)$mycanmb7ctrl = 0x0088
set *(unsigned short *)$mycanmb8ctrl = 0x0088
set *(unsigned short *)$mycanmb9ctrl = 0x0000
set *(unsigned short *)$mycanmb10ctrl = 0x0000
set *(unsigned short *)$mycanmb11ctrl = 0x0000
set *(unsigned short *)$mycanmb12ctrl = 0x0000
set *(unsigned short *)$mycanmb13ctrl = 0x0000
set *(unsigned short *)$mycanmb14ctrl = 0x0000
set *(unsigned short *)$mycanmb15ctrl = 0x0000


# FRZ 0x4000 HALT 0x1000 SELFWAKE  0x40
set *(unsigned long *)$mycanrxgmask = 0xFFE00000

# FRZ 0x4000 HALT SELFWAKE  0x40
set *(unsigned short *)$mycanmcr = 0x4040


end

define setup_gpio

set *(unsigned char *)$mypbcdpar=0xC0
set *(unsigned char *)$mypuapar=0x0F
set *(unsigned char *)$mypjpar=0xFF

end

define setup_iram
####### set up internal sram ####################
set *$myrambar = 0x20000200

if 0
set *0x20000000=0x12345678
set *0x20000000=0x55aa55aa
set *0x20000004=0xaa55aa55
x 0x20000000
x 0x20000004
end
# end setup_iram
end


####### set up pll ####################
define setup_pll
#set $myclocksyncr = $myipsbar -1 + 0x120000    
#set $myclocksynsr = $myipsbar -1 + 0x120002    

set *(unsigned short *)$myclocksyncr =  (((2)&0x0007)<<12)  
   
while ((*$myclocksynsr &  0x08000000) == 0 )
	set $foo = 0
end

# end setup_pll
end

######### set up uart 0 ###########################

define setup_uart0

#set $mygpio_puapar = $myipsbar -1 + 0x10005C    
#set $myuart0_umr   = $myipsbar -1 + 0x200    
#set $myuart0_ucsr  = $myipsbar -1 + 0x204    
#set $myuart0_ucr   = $myipsbar -1 + 0x208    
#set $myuart0_utb   = $myipsbar -1 + 0x20c    
#set $myuart0_urb   = $myipsbar -1 + 0x20c    
#set $myuart0_uimr  = $myipsbar -1 + 0x214    
#set $myuart0_ubg1  = $myipsbar -1 + 0x218    
#set $myuart0_ubg2  = $myipsbar -1 + 0x21c    

set *(unsigned char *)$mygpio_puapar=0x0f
#reset tx
set *(unsigned char *)$myuart0_ucr=0x30
#reset rx
set *(unsigned char *)$myuart0_ucr=0x20
#reset mr
set *(unsigned char *)$myuart0_ucr=0x10

# no parity 8 bits per char
set *(unsigned char *)$myuart0_umr=0x13

# no echo or loopback 1 stop
set *(unsigned char *)$myuart0_umr=0x07
 
# rx tx baud by timer
set *(unsigned char *)$myuart0_ucsr=0xdd

# mask all interrupts
set *(unsigned char *)$myuart0_uimr=0x0

set $uast_brg = (64000000/(19200 * 32))

# set up baud rates
set *(unsigned char *)$myuart0_ubg1=($uast_brg & 0xFF00) >> 8
set *(unsigned char *)$myuart0_ubg2=($uast_brg & 0x00FF)

# enable tx rx
set *(unsigned char *)$myuart0_ucr=0x5

#end uart0
end

define send_chars
# send chars
set *(unsigned char *)$myuart0_utb=0x41
set *(unsigned char *)$myuart0_utb=0x42
set *(unsigned char *)$myuart0_utb=0x43
set *(unsigned char *)$myuart0_utb=0x44
#end send_chars
end


define setup_cs
######### set up CS (just fsram and flash)###########################

#set $mycs0_csar   = $myipsbar -1 + 0x80    
#set $mycs0_csmr   = $myipsbar -1 + 0x84    
#set $mycs0_cscr   = $myipsbar -1 + 0x8A    

#set $mycs1_csar   = $myipsbar -1 + 0x8C    
#set $mycs1_csmr   = $myipsbar -1 + 0x90    
#set $mycs1_cscr   = $myipsbar -1 + 0x96    

#set $mycs2_csar   = $myipsbar -1 + 0x98    
#set $mycs2_csmr   = $myipsbar -1 + 0x9C    
#set $mycs2_cscr   = $myipsbar -1 + 0xA2    

#set $mycs3_csar   = $myipsbar -1 + 0xA4    
#set $mycs3_csmr   = $myipsbar -1 + 0xA8    
#set $mycs3_cscr   = $myipsbar -1 + 0xAE    

#set $mycs4_csar   = $myipsbar -1 + 0xB0    
#set $mycs4_csmr   = $myipsbar -1 + 0xB4    
#set $mycs4_cscr   = $myipsbar -1 + 0xBA    

#set $mycs5_csar   = $myipsbar -1 + 0xBC    
#set $mycs5_csmr   = $myipsbar -1 + 0xC0    
#set $mycs5_cscr   = $myipsbar -1 + 0xC6    

#set $mycs6_csar   = $myipsbar -1 + 0xC8    
#set $mycs6_csmr   = $myipsbar -1 + 0xCC    
#set $mycs6_cscr   = $myipsbar -1 + 0xD2   


# ide from 3200_0000 6 ws
set *(unsigned short *)$mycs2_csar=0x3200
set *(unsigned short *)$mycs2_cscr=0x1980
set *(unsigned long *) $mycs2_csmr=0x00070001

# 512K 32 bit fsram  starting at 0x3000_0000 1 WS ??
set *(unsigned short *)$mycs1_csar=0x3000
set *(unsigned short *)$mycs1_cscr=0x0100
set *(unsigned long *) $mycs1_csmr=0x00070001

if 0
# flash
set *(unsigned short *)$mycs0_csar=0xFFE0
set *(unsigned short *)$mycs0_cscr=0x1980
set *(unsigned long *) $mycs0_csmr=0x001f0001
end

#end setup_cs
end


####################################################
define setup_sdram
######### set up SDRAM ###########################

#set $mysdramc_dcr     = $myipsbar -1 + 0x40    
#set $mysdramc_dacr0   = $myipsbar -1 + 0x48
#set $mysdramc_dmr0    = $myipsbar -1 + 0x4C
#set $mysdramc_dacr1   = $myipsbar -1 + 0x50
#set $mysdramc_dmr1    = $myipsbar -1 + 0x54



#
# some delay
#
set $foo = 0
# in c use 20000
  while ($foo < 20000)
	set $foo += 1
  end

if 1
# if ( !($mysdramc_dacr0 & 0x00008000))
   #
   # init dram cr get it into the high short
   set * $mysdramc_dcr   = \
	(0x0200 | (((15 * 64)>>4)& 0x01ff)) << 16

   # init dacr0
   #	
   set * $mysdramc_dacr0 = \
	(0x00000000 & 0xfffc0000) | (((2)&0x03)<<12) |(((3)&0x07)<<8) | 0x0
 

   #
   # init dmr0
   set * $mysdramc_dmr0 = \
 	0 | (0x00FC0000) |  (0x00000001)

   #
   # set ip ( bit 3 ) in dacr
   set * $mysdramc_dacr0 |= (0x00000008)  

   #
   # init precharge
   set *(0x00000000) = 0xA5A59696

   #
   # wait
   while ($foo < 20000)
	set $foo += 1
   end

   #
   # set RE  in dacr
   set * $mysdramc_dacr0 |= \
	(0x00008000)  
   #
   # issue IMRS
   set * $mysdramc_dacr0 |= \
	(0x00000040)  

   #
   # wait for 8 auto refresh
   while ($foo < 20000)
	set $foo += 1
   end
   #
   # set mode
   set *(0x00000000 + 0x400 ) = 0xA5A59696

  # end if 1
  end
#end setup_sdram
end


addresses
#setup_gpio
setup_iram
#setup_pll
#setup_uart0
#send_chars
setup_cs
#setup_sdram
#setup_can

bdm_setdelay 100
bdm_no_wait
#bdm-no-load
bdm_reset
continue
bdm_stop
#bdm_wait
#load
run