case 6:
     printf(" MicroBoone PMT link test routine \n");
//     printf(" enter time size \n");
//     scanf("%d",&timesize);
     printf(" number of event\n");
     scanf("%d",&nevent);
     ihuff =0;  // no huffman encoding -- need to predict event size
     itrif_ext = 1;
     use_pmt =1;
     pmt_testpulse =0;
     icont =0;
     imulti=0;
//
//

// 
//
     printf("type 1 to write the data to file \n");
     scanf("%d", iwrite);

     idebug == 1;
//     iwrite == 0;
     irawprint == 1;
     dwDMABufSize ==100000;
//     printf("type 1 for print out debug information in dma loop\n");
//     scanf("%d",&idebug);
//     printf(" type 1 to write data to fiile \n");
//     scanf("%d", &iwrite);
//     printf("type 1 for raw data print \n");
//     scanf("%d",&irawprint);
//     printf(" enter buffer size in bytes \n");
//     scanf("%d",&dwDMABufSize);
//     printf(" enter 1 to check last word \n");
//     scanf("%d",&ilast_check);
//     printf(" enter 1 for wait loop \n");
//     scanf("%d",&iwait_loop);
//     if(iwait_loop == 1) {
//       printf(" enter wait time in microsec unit \n");
//       scanf("%d",&iwait_usec);
//     }
     printf(" xmit module address \n");
     scanf("%d",&imod_xmit);
     printf(" slot address of the 1st FEM module \n");
     scanf("%d",&imod_st);
     printf(" number of FEM = %d\n",(imod_st - imod_xmit));
//     printf(" type 1 for neutrino event, 2 for superNova \n");
//     scanf("%d",&itrig_type);
//
//
//
     imod_trig = 18;
     imod_shaper =4;
     itrig_delay = 51;
//     imod_fem = 11;
     printf(" PMT ADC module address = %d \n", imod_fem);
     printf(" Shaper address = %d \n", imod_shaper);
     printf(" Trigger module address = %d \n", imod_trig);

     if(iwrite == 1) {
      fd = creat("test123.dat",0755);
      printf("fd = %d \n", fd);
     }
     iframe_length = 8191;
     iframe = iframe_length;
//     iframe_length = 25599;
     itrig_delay = 10;
//     timesize =2000;
//     timesize =200;
//     dwDMABufSize = 1500000;
     printf(" frame size = %d\n", iframe_length);
//     timesize = 3199;

//     printf(" 1 for checking the event \n");
//     scanf("%d",&icheck);
//     printf(" type 1 to use random number \n");
//     scanf("%d",&irand);
     icheck =0;
     ifr=0;
     irand = 0;
     islow_read =0;
//     if(icheck != 1) {
//      printf(" 1 for print event\n");
//      scanf("%d",&iprint);
//    }
//     else iprint =0;
     iprint = 1;
//     printf(" number event \n");
//     scanf("%d",&nevent);

//     printf(" enter number of words per packet \n");
//     scanf("%d",&nsend);
     nsend=500;
//     imod_xmit=10;

// once the fpga is booted we should let system receive fill frame before send any data.
// set system with normal transmitter mode

     dwAddrSpace =2;
     u32Data = 0x20000000;    // initial transmitter, no hold
     dwOffset = 0x18;
     WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
     dwAddrSpace =2;
     u32Data = 0x20000000;    // initial transmitter, no hold
     dwOffset = 0x20;
     WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);

     dwAddrSpace =2;
     u32Data = 0x20000000;    // initial receiver
     dwOffset = 0x1c;
     WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
     dwAddrSpace =2;
     u32Data = 0x20000000;   // initial receiver
     dwOffset = 0x24;
     WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);


     dwAddrSpace =2;
     u32Data = 0xfff;    // set mode off with 0xfff...
     dwOffset = 0x28;
     WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);

//
//
//
     px = &buf_send;
     py = &read_array;
     imod =0;  /* controller module */
/** initialize **/
     buf_send[0]=0x0;
     buf_send[1]=0x0;
     i=1;
     k=1;
     i = pcie_send(hDev, i, k, px);
// set offline test
     imod=0;
     ichip=1;
     buf_send[0]=(imod<<11)+(ichip<<8)+(mb_cntrl_test_on)+(0x0<<16); //enable offline run on
     i=1;
     k=1;
     i = pcie_send(hDev, i, k, px);
 //disable the run command
     imod=0;
     ichip=1;
     buf_send[0]=(imod<<11)+(ichip<<8)+(mb_cntrl_set_run_off)+(0x0<<16); //trun off run
     i=1;
     k=1;
     i = pcie_send(hDev, i, k, px);
 //
 //
 //
     if(itrig_ext == 1) {
 //
 //  set trigger module run off
 //
      imod=imod_trig;
      buf_send[0]=(imod<<11)+(mb_trig_run)+((0x0)<<16); //set up run off
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);
 //
 //  set trigger module dead time size
 //
      imod=imod_trig;
      buf_send[0]=(imod<<11)+(mb_trig_deadtime_size)+(0x1<<16); //set trigger module deadtime size
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);
 // set offline test
      imod=0;
      ichip=1;
      buf_send[0]=(imod<<11)+(ichip<<8)+(mb_cntrl_test_off)+(0x0<<16); //set controller test off
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);

     }
     else {
//
//disable the run command
//
      imod=0;
      ichip=1;
      buf_send[0]=(imod<<11)+(ichip<<8)+(mb_cntrl_set_run_off)+(0x0<<16); //enable offline run on
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);
//
// load trig 1 position relative to the frame..
//
      imod=0;
      ichip=1;
      buf_send[0]=(imod<<11)+(ichip<<8)+(mb_cntrl_load_trig_pos)+((itrig_delay & 0xffff)<<16); //enable test mode
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);
     }


//     printf(" enable number of loop\n");
//     scanf("%d",&nloop);
//
//   starting boot process
//
//
//    boot up xmit module 1st
//
     printf(" boot xmit module \n");
     inpf = fopen("/home/ub/xmit_fpga_link_header","r");
     imod=imod_xmit;
     ichip=mb_xmit_conf_add;
     buf_send[0]=(imod<<11)+(ichip<<8)+0x0+(0x0<<16);  // turn conf to be on
     i=1;
     k=1;
     i = pcie_send(hDev, i, k, px);
//      for (i=0; i<100000; i++) {
//          ik= i%2;
//          dummy1= (ik+i)*(ik+i);
//      }


       /* read data as characters (28941) */
     usleep(1000);   // wait fior a while
     count = 0;
     counta= 0;
     ichip_c = 7; // set ichip_c to stay away from any other command in the
     dummy1 =0;
     while (fread(&charchannel,sizeof(char),1,inpf)==1) {
      carray[count] = charchannel;
      count++;
      counta++;
      if((count%(nsend*2)) == 0) {
//        printf(" loop = %d\n",dummy1);
       buf_send[0] = (imod <<11) +(ichip_c <<8)+ (carray[0]<<16);
       send_array[0] =buf_send[0];
       if(dummy1 <= 5 ) printf(" counta = %d, first word = %x, %x, %x %x %x \n",counta,buf_send[0], carray[0], carray[1]
       ,carray[2], carray[3]);
       for (ij=0; ij< nsend; ij++) {
        if(ij== (nsend-1)) buf_send[ij+1] = carray[2*ij+1]+(0x0<<16);
        else buf_send[ij+1] = carray[2*ij+1]+ (carray[2*ij+2]<<16);
//         buf_send[ij+1] = carray[2*ij+1]+ (carray[2*ij+2]<<16);
        send_array[ij+1] = buf_send[ij+1];
       }
       nword =nsend+1;
       i=1;
//       if(dummy1 == 0)
       ij = pcie_send(hDev, i, nword, px);
       nanosleep(&tim , &tim2);
       dummy1 = dummy1+1;
       count =0;
      }
     }
     if(feof(inpf)) {
      printf("You have reached the end-of-file word count= %d %d\n", counta, count);
      buf_send[0] = (imod <<11) +(ichip_c <<8)+ (carray[0]<<16);
      if ( count > 1) {
       if( ((count-1)%2) ==0) {
        ik =(count-1)/2;
       }
       else {
        ik =(count-1)/2+1;
       }
       ik=ik+2;   // add one more for safety
       printf("ik= %d\n",ik);
       for (ij=0; ij<ik; ij++){
        if(ij == (ik-1)) buf_send[ij+1] = carray[(2*ij)+1]+(((imod<<11)+(ichip<<8)+0x0)<<16);
        else buf_send[ij+1] = carray[(2*ij)+1]+ (carray[(2*ij)+2]<<16);
        send_array[ij+1] = buf_send[ij+1];
       }
      }
      else ik=1;
      for (ij=ik-10; ij< ik+1; ij++) {
        printf("Last data = %d, %x\n",ij,buf_send[ij]);
      }
      nword =ik+1;
      i=1;
      i = pcie_send(hDev, i, nword, px);
     }
     usleep(2000);    // wait for 2ms to cover the packet time plus fpga init time
     fclose(inpf);
//
     printf(" xmit done, booting FEM \n");
     scanf("%d",&ik);

//
//   *********************************************************************************
//

     imod_last = imod_xmit+1;
     for (imod_fem = imod_last; imod_fem< (imod_st+1); imod_fem++) {
      printf(" booting FEM module %d \n",imod_fem);
      scanf("%d",&ik);
      ik=pmt_adc_setup(hDev,imod_fem,iframe);
     }

//
//    both FEM and XMIT bootted.
//
//
//   /* set tx mode register */
//
     u32Data = 0x00003fff;  // set up number of words hold coming back from the XMIT module
     printf(" number of words for hold be send back = %x\n",u32Data);
     dwOffset = 0x28;
     dwAddrSpace =2;
     WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
//
//   set up hold
//
     printf(" set up the hold condition \n");
     dwAddrSpace =2;
     u32Data = 0x8000000;    // set up transmitter to return the hold -- upper transciever
     dwOffset = 0x18;
     WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
     dwAddrSpace =2;
     u32Data = 0x8000000;    // set up transmitter to return the hold -- lower transciever
     dwOffset = 0x20;
     WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
//
//
     if(itrig_ext == 1) {
      imod=imod_trig;
//      iframe= 511;    //1023
      buf_send[0]=(imod<<11)+(mb_trig_frame_size)+((iframe & 0xffff)<<16); //set up frame size.
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);
     }
     else {
//
// set frame set to be 1023 --- there will be 1023/8 = 128 adc samples.
//
      imod=0;
      ichip=1;
//      iframe= 511;    //1024
      buf_send[0]=(imod<<11)+(ichip<<8)+(mb_cntrl_load_frame)+((iframe & 0xffff)<<16); // set frame length
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);
     }
//
//
//
     if(itrig_ext == 1) {
//
//    set mask1 bit 3 high
//
      imod=imod_trig;
      buf_send[0]=(imod<<11)+(mb_trig_mask1)+(0x8<<16); //set mask1[3] on.
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);
//
//    set prescale1 to 0
//
      imod=imod_trig;
      buf_send[0]=(imod<<11)+(mb_trig_prescale1)+(0x0<<16); //set prescale1 0
      i=1;
      k=1;
      i = pcie_send(hDev, i, k, px);
     }

//

//
//
//  ****************************************
//
      printf(" call pmt_link \n");
      ik = pmt_link_setup(hDev,imod_xmit,imod_st,0);      // no supernova
//
//      turn the run on to start data flow
//
      printf(" enter 1 to set the RUN on \n");
      scanf("%d",&ik);
//
//
      ifr=0;
//
      for (ib=0; ib<nevent; ib++) {
//
//
       if(ifr ==0) {
//         ifr=1;
        printf(" buffer allocation 1\n");
        dwDMABufSize = 60000;
        dwStatus = WDC_DMAContigBufLock(hDev1, &pbuf_rec, dwOptions_rec, dwDMABufSize, &pDma_rec);
        if (WD_STATUS_SUCCESS != dwStatus) {
         printf("Failed locking a rec Contiguous DMA buffer. Error 0x%lx - %s\n", dwStatus, Stat2Str(dwStatus));
         printf("enter 1 to continue \n");
         scanf("%d",&is);
        }
        else {
         u32Data = pDma_rec->Page->pPhysicalAddr & 0xffffffff;
         printf(" buffer allocation lower address = %x\n", u32Data);
         u32Data = (pDma_rec->Page->pPhysicalAddr >> 32) & 0xffffffff;
         printf(" buffer allocation higher address = %x\n", u32Data);
        }
/* set tx mode register */

        u32Data = 0x00002000;
        dwOffset = tx_md_reg;
        dwAddrSpace =cs_bar;
        WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);

         /* write this will abort previous DMA */
        dwAddrSpace =2;
        dwOffset = cs_dma_msi_abort;
        u32Data = dma_abort;
        WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
/* clear DMA register after the abort */
        dwAddrSpace =2;
        dwOffset = cs_dma_msi_abort;
        u32Data = 0;
        WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
        printf(" initial abort finished \n");
       }

       buffp_rec32 = pbuf_rec;
       if(icont == 1) nwrite_byte = ibytec;
       else nwrite_byte = dwDMABufSize;
       for (is=0; is< nwrite_byte/4; is++) {
         buffp_rec32[is]=0;
       }
//
//
       for (is=1; is<3; is++) {
        tr_bar = t1_tr_bar;
        r_cs_reg = r1_cs_reg;
        dma_tr = dma_tr1;
        if(is == 2) {
         tr_bar = t2_tr_bar;
         r_cs_reg = r2_cs_reg;
         dma_tr = dma_tr2;
        }
        if(idebug ==1) printf(" is = %d\n",is);
/** initialize the receiver ***/
        u32Data = cs_init;
        dwOffset = r_cs_reg;
        dwAddrSpace =cs_bar;
//
// rreceiver only get initialize for the 1st time
//
//
//        if(ifr ==0) {
         if(icont != 1) printf(" initialize the input fifo\n");
         WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
//        }
/** start the receiver **/
        dwAddrSpace = cs_bar;
//        u32Data = cs_start+(nwrite*2)*4;   /* 32 bits mode == 4 bytes per word *2 fibers **/
        u32Data = cs_start+nwrite_byte;   /* 32 bits mode == 4 bytes per word *2 fibers **/
//**         if(iwrite != 1) printf(" DMA loop %d with DMA data length %d \n", iv, nwrite_byte);
        dwOffset = r_cs_reg;
        WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
       }
       ifr=1;
//        if((ifr ==0) &&(idebug ==1)) printf(" initial receiver \n");
//       scanf("%d",&ik);
/** set up DMA for both transceiver together **/

       dwAddrSpace =cs_bar;
       dwOffset = cs_dma_add_low_reg;
       u32Data = pDma_rec->Page->pPhysicalAddr & 0xffffffff;
       WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);

       dwAddrSpace =cs_bar;
       dwOffset = cs_dma_add_high_reg;
       u32Data = (pDma_rec->Page->pPhysicalAddr >> 32) & 0xffffffff;
       WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);

/* byte count */
       dwAddrSpace =cs_bar;
       dwOffset = cs_dma_by_cnt;
//        u32Data = (nwrite)*4*2;      /** twice more data - from fiber 1& 2**/
       u32Data = nwrite_byte;
       WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);


/* write this will start DMA */
       dwAddrSpace =2;
       dwOffset = cs_dma_cntrl;
       is = (pDma_rec->Page->pPhysicalAddr >> 32) & 0xffffffff;
       if(is == 0) {
//**         if(iwrite !=1 ) printf(" use 3dw \n");
        u32Data = dma_tr12+dma_3dw_rec;
       }
       else {
        u32Data = dma_tr12+dma_4dw_rec;
//**        if(iwrite !=1 ) printf(" use 4dw \n");
       }
       WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
//       if(idebug ==1)
       if(icont != 1) printf(" DMA set up done, byte count = %d\n", nwrite_byte);

//
//
//
       if(itrig_ext ==1) {
//
//     only need to restart the run if the we use the test data or 1st run
//
        if((ib == 0)|| (use_pmt != 1)) {
         imod=imod_trig;
         buf_send[0]=(imod<<11)+(mb_trig_run)+((0x1)<<16); //set up run
         i=1;
         k=1;
         i = pcie_send(hDev, i, k, px);
        }

        imod = imod_trig;
        buf_send[0]=(imod<<11)+(mb_trig_pctrig)+(0x1<<16); // fire pc trig
        i=1;
        k=1;
        i = pcie_send(hDev, i, k, px);
       }



       printf(" trigger send \n");
       if(irawprint==1) scanf("%d", &i);
//
//     wait for trigger to be processed and data send to pc.
//
       usleep(6000);
//
//
//
       if(icont == 1) {
        idone = 0;
/***    check to see if DMA is done or not **/
        for (is=0; is<6000000; is++) {
         dwAddrSpace =cs_bar;
         u64Data =0;
         dwOffset = cs_dma_cntrl;
         WDC_ReadAddr32(hDev1, dwAddrSpace, dwOffset, &u32Data);
//         if(idebug ==1) printf(" receive DMA status word %d %X \n", is, u32Data);
         if((u32Data & dma_in_progress) == 0) {
           idone =1;
         }
         if((u32Data & dma_in_progress) == 0) break;
        }
        if(idone ==0) printf("DMA is not done \n");
        for (is=0; is < (nwrite_byte/4); is++) {
         if((is%8) ==0) printf("%4d",is);
         printf("  %8X", buffp_rec32[is]);
         if((is+1)%8 ==0) printf("\n");
        }
        if((is+1)%8 !=0) printf("\n");
       }

       else {
        usleep(6000);
        printf("nwrite_byte = %d %x\n", nwrite_byte, nwrite_byte);
        nremain_tran1=0;
        idone=0;
        for(i=0; i< 1000000; i++) {
         usleep(80000);                     // have to wait long enough for other board data show up
         dwAddrSpace =cs_bar;
         u64Data =0;
         dwOffset = t1_cs_reg;
         WDC_ReadAddr64(hDev1, dwAddrSpace, dwOffset, &u64Data);
         u32Data=u64Data;
         printf (" transmitter 1 loop %d status = %8X \n",i,u32Data);
         u32Data=u64Data>>32;
         printf (" receiver 1 loop %d status = %8X \n",i,u32Data);
         if(nremain_tran1 == u32Data) idone=1;
         else nremain_tran1 = u32Data;
         if(idone ==1) break;
        }

        dwAddrSpace =cs_bar;
        dwOffset = cs_dma_by_cnt;
        WDC_ReadAddr64(hDev1, dwAddrSpace, dwOffset, &u64Data);
        printf(" DMA word count before abort = %8x %8x \n",(u64Data>> 32), (u64Data & 0xffffffff));
        printf(" register data load is %8x \n", nwrite_byte);
        nread_dma = u64Data & 0xfffffff;
//
//
//
        dwAddrSpace =cs_bar;
        dwOffset = t1_cs_reg;
        WDC_ReadAddr64(hDev1, dwAddrSpace, dwOffset, &u64Data);
        u32Data=u64Data>>32;
        printf (" receiver 1 status = %8X \n",u32Data);
//
//
        dwAddrSpace =cs_bar;
        dwOffset = t2_cs_reg;
        WDC_ReadAddr64(hDev1, dwAddrSpace, dwOffset, &u64Data);
        u32Data=u64Data>>32;
        printf (" receiver 2 status = %8X \n",u32Data);
//
//
//
/*
       for (is=0; is< (((nwrite_byte-nread_dma)/4)+8); is++) {
         if((is%8) ==0) printf("%4d",is);
         printf("  %8X", buffp_rec32[is]);
         if((is+1)%8 ==0) printf("\n");
       }
*/
        WDC_DMASyncCpu(pDma_rec);
        WDC_DMASyncIo(pDma_rec);
        ik= (nwrite_byte-nread_dma)/4;
        nremain = (nwrite_byte - (nremain_tran1 &0xffff)) - (nwrite_byte- nread_dma);
        printf(" nremain = %d, nremain/4 = %d \n", nremain, nremain/4);

        for (is =0; is < ik; is++) {
         read_array[is] = *buffp_rec32++;
        }

        scanf("%d",&is);

        for (is=0; is< ((nremain/8)+4); is++) {
         dwAddrSpace = t1_tr_bar;
         u64Data =0;
         dwOffset =0;
         WDC_ReadAddr64(hDev1, dwAddrSpace, dwOffset, &u64Data);
         u32Data =   (u64Data>> 32) & 0xffffffff;
//         buffp_rec32[ik+is*2+1] = u32Data;
         read_array[ik+is*2+1] = u32Data;
//         printf(" %d u64Data =  %8X ", is , u32Data);
         u32Data =   u64Data& 0xffffffff;
//         buffp_rec32[ik+is*2] = u32Data;
         read_array[ik+is*2] = u32Data;
//         printf(" %8X \n", u32Data);
        }
        for (is=0; is < (((nwrite_byte - (nremain_tran1 & 0xffff))/4)+8); is++) {
         if((is%8) ==0) printf("%4d",is);
         printf("  %8X", read_array[is]);
         if((is+1)%8 ==0) printf("\n");
        }

/*
      for (is=0; is< ((nremain/8)+4); is++) {
         dwAddrSpace = t1_tr_bar;
         u64Data =0;
         dwOffset =0;
         WDC_ReadAddr32(hDev1, dwAddrSpace, dwOffset, &u32Data);
         printf(" %d u64Data =  %8X \n", is , u32Data);
       }
*/
//
//     set up abort
//
         /* write this will abort previous DMA */
        dwAddrSpace =2;
        dwOffset = cs_dma_msi_abort;
        u32Data = dma_abort;
        WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
/* clear DMA register after the abort */
        dwAddrSpace =2;
        dwOffset = cs_dma_msi_abort;
        u32Data = 0;
        WDC_WriteAddr32(hDev1, dwAddrSpace, dwOffset, u32Data);
        printf(" initial abort finished \n");
        scanf("%d",&ik);
       }

      }
     break;




//    } //&&&&&&&&&&&&&&&&&&&