// megafunction wizard: %ALTOCT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALT_OCT 

// ============================================================
// File Name: a_oct.v
// Megafunction Name(s):
// 			ALT_OCT
//
// Simulation Library Files(s):
// 			altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2.30 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//alt_oct CBX_AUTO_BLACKBOX="ALL" device_family="Stratix III" ENABLE_PARALLEL_TERMINATION="FALSE" OCT_BLOCK_NUMBER=1 cal_shift_busy calibration_busy calibration_request clock parallelterminationcontrol rdn rup s2pload seriesterminationcontrol
//VERSION_BEGIN 9.1SP2 cbx_alt_oct 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463


//synthesis_resources = lpm_counter 6 reg 9 stratixiii_termination 1 stratixiii_termination_logic 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  a_oct_alt_oct_n8n
	( 
	cal_shift_busy,
	calibration_busy,
	calibration_request,
	clock,
	parallelterminationcontrol,
	rdn,
	rup,
	s2pload,
	seriesterminationcontrol,
	shift_busy) ;
	output   [0:0]  cal_shift_busy;
	output   [0:0]  calibration_busy;
	input   [0:0]  calibration_request;
	input   clock;
	output   [13:0]  parallelterminationcontrol;
	input   [0:0]  rdn;
	input   [0:0]  rup;
	input   [0:0]  s2pload;
	output   [13:0]  seriesterminationcontrol;
	output   [0:0]  shift_busy;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   [0:0]  calibration_request;
	tri0   clock;
	tri0   [0:0]  s2pload;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	reg	aclruser_dffe;
	reg	[0:0]	cal_shift_busy_dffe;
	reg	[0:0]	calibration_busy_dffe;
	reg	[0:0]	calibration_busy_only_dffe;
	reg	clkenuser_dffe;
	reg	[0:0]	e;
	wire	wire_e_ena;
	reg	[0:0]	serializer_enables_dffe;
	reg	[0:0]	serializer_only_enables_dffe;
	reg	[0:0]	shift_only_busy_dffe;
	wire  [2:0]   wire_cntr3_q;
	wire  wire_cntr4_cout;
	wire  wire_cntr5_cout;
	wire  wire_cntr6_cout;
	wire  [1:0]   wire_cntr8_q;
	wire  wire_cntr9_cout;
	wire  [0:0]   wire_sd1a_serializerenable;
	wire  [0:0]   wire_sd1a_serializerenableout;
	wire  [0:0]   wire_sd1a_terminationcontrol;
	wire  [13:0]   wire_sd2a_0parallelterminationcontrol;
	wire  [13:0]   wire_sd2a_0seriesterminationcontrol;
	wire  [0:0]  a;
	wire aclr;
	wire  aclruser;
	wire  [0:0]  cal_shift_busy_t;
	wire  [0:0]  calibration_busy_t;
	wire [0:0]  calibration_only_req;
	wire [0:0]  calibration_wait;
	wire  calibration_wait_or;
	wire clken;
	wire  clkenuser;
	wire  during_calibration_only;
	wire  during_shift_only;
	wire  [0:0]  priority_main;
	wire  priority_star_or;
	wire  [9:0]  serializer_enables;
	wire [0:0]  shift_only_req;
	wire  state_counter_enable;
	wire  state_counter_start;
	wire  [0:0]  sub_aclruser;
	wire  [0:0]  sub_clkenuser;
	wire  [0:0]  sub_state_counter_enable;
	wire  [0:0]  sub_state_counter_start;

	// synopsys translate_off
	initial
		aclruser_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) aclruser_dffe <= 1'b0;
		else if  (clken == 1'b1)   aclruser_dffe <= ((((~ wire_cntr3_q[2]) & wire_cntr3_q[1]) & (~ wire_cntr3_q[0])) | sub_aclruser[0]);
	// synopsys translate_off
	initial
		cal_shift_busy_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) cal_shift_busy_dffe <= 1'b0;
		else if  (clken == 1'b1)   cal_shift_busy_dffe <= (((wire_cntr3_q[2] | wire_cntr3_q[1]) | wire_cntr3_q[0]) & e);
	// synopsys translate_off
	initial
		calibration_busy_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) calibration_busy_dffe <= 1'b0;
		else if  (clken == 1'b1)   calibration_busy_dffe <= ((((((((~ wire_cntr3_q[2]) & (~ wire_cntr3_q[1])) & wire_cntr3_q[0]) | (((~ wire_cntr3_q[2]) & wire_cntr3_q[1]) & (~ wire_cntr3_q[0]))) | (((~ wire_cntr3_q[2]) & wire_cntr3_q[1]) & wire_cntr3_q[0])) | ((wire_cntr3_q[2] & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[0]))) | ((wire_cntr3_q[2] & (~ wire_cntr3_q[1])) & wire_cntr3_q[0])) & e);
	// synopsys translate_off
	initial
		calibration_busy_only_dffe[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) calibration_busy_only_dffe[0:0] <= 1'b0;
		else  calibration_busy_only_dffe[0:0] <= (wire_cntr8_q[1] | wire_cntr8_q[0]);
	// synopsys translate_off
	initial
		clkenuser_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) clkenuser_dffe <= 1'b0;
		else if  (clken == 1'b1)   clkenuser_dffe <= ((((((~ wire_cntr3_q[2]) & wire_cntr3_q[1]) & (~ wire_cntr3_q[0])) | (((~ wire_cntr3_q[2]) & wire_cntr3_q[1]) & wire_cntr3_q[0])) | ((wire_cntr3_q[2] & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[0]))) | sub_clkenuser[0]);
	// synopsys translate_off
	initial
		e = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) e <= 1'b0;
		else if  (wire_e_ena == 1'b1)   e <= ((calibration_request & (~ wire_cntr3_q[2])) | (((wire_cntr3_q[2] & wire_cntr3_q[1]) & (~ wire_cntr3_q[0])) & (e ^ priority_main)));
	assign
		wire_e_ena = (clken & ((((~ wire_cntr3_q[0]) & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[2])) | (((wire_cntr3_q[2] & wire_cntr3_q[1]) & (~ wire_cntr3_q[0])) & wire_cntr4_cout)));
	// synopsys translate_off
	initial
		serializer_enables_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) serializer_enables_dffe <= 1'b0;
		else if  (clken == 1'b1)   serializer_enables_dffe <= ((((e & (~ wire_cntr3_q[2])) & wire_cntr3_q[1]) & wire_cntr3_q[0]) | (((priority_main & wire_cntr3_q[2]) & wire_cntr3_q[1]) & (~ wire_cntr3_q[0])));
	// synopsys translate_off
	initial
		serializer_only_enables_dffe[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) serializer_only_enables_dffe[0:0] <= 1'b0;
		else if  (clken == 1'b1)   serializer_only_enables_dffe[0:0] <= ((wire_cntr8_q[1] & (~ wire_cntr8_q[0])) | shift_only_busy_dffe);
	// synopsys translate_off
	initial
		shift_only_busy_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) shift_only_busy_dffe <= 1'b0;
		else  shift_only_busy_dffe <= (((shift_only_req & sub_state_counter_start) | shift_only_busy_dffe) & (~ wire_cntr6_cout));
	lpm_counter   cntr3
	( 
	.aclr(aclr),
	.clk_en(state_counter_enable),
	.clock(clock),
	.cout(),
	.data(3'b110),
	.eq(),
	.q(wire_cntr3_q),
	.sload((((wire_cntr3_q[2] & wire_cntr3_q[1]) & wire_cntr3_q[0]) & priority_star_or))
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.sclr(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr3.lpm_port_updown = "PORT_UNUSED",
		cntr3.lpm_width = 3,
		cntr3.lpm_type = "lpm_counter";
	lpm_counter   cntr4
	( 
	.aclr(aclr),
	.clk_en(((wire_cntr3_q[2] & wire_cntr3_q[1]) & (~ wire_cntr3_q[0]))),
	.clock(clock),
	.cout(wire_cntr4_cout),
	.eq(),
	.q()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({5{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr4.lpm_modulus = 28,
		cntr4.lpm_port_updown = "PORT_UNUSED",
		cntr4.lpm_width = 5,
		cntr4.lpm_type = "lpm_counter";
	lpm_counter   cntr5
	( 
	.aclr(aclr),
	.clk_en((((~ wire_cntr3_q[2]) & wire_cntr3_q[1]) & wire_cntr3_q[0])),
	.clock(clock),
	.cout(wire_cntr5_cout),
	.eq(),
	.q()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({8{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr5.lpm_modulus = 200,
		cntr5.lpm_port_updown = "PORT_UNUSED",
		cntr5.lpm_width = 8,
		cntr5.lpm_type = "lpm_counter";
	lpm_counter   cntr6
	( 
	.aclr(aclr),
	.clk_en(during_shift_only),
	.clock(clock),
	.cout(wire_cntr6_cout),
	.eq(),
	.q()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({5{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr6.lpm_modulus = 28,
		cntr6.lpm_port_updown = "PORT_UNUSED",
		cntr6.lpm_width = 5,
		cntr6.lpm_type = "lpm_counter";
	lpm_counter   cntr8
	( 
	.aclr(aclr),
	.clk_en(sub_state_counter_enable[0]),
	.clock(clock),
	.cout(),
	.data({2{1'b0}}),
	.eq(),
	.q(wire_cntr8_q),
	.sload((wire_cntr8_q[1] & wire_cntr8_q[0]))
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.sclr(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr8.lpm_port_updown = "PORT_UNUSED",
		cntr8.lpm_width = 2,
		cntr8.lpm_type = "lpm_counter";
	lpm_counter   cntr9
	( 
	.aclr(aclr),
	.clock(clock),
	.cnt_en((wire_cntr8_q[1] | wire_cntr8_q[0])),
	.cout(wire_cntr9_cout),
	.eq(),
	.q()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.clk_en(1'b1),
	.data({8{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr9.lpm_modulus = 200,
		cntr9.lpm_port_updown = "PORT_UNUSED",
		cntr9.lpm_width = 8,
		cntr9.lpm_type = "lpm_counter";
	stratixiii_termination   sd1a_0
	( 
	.incrdn(),
	.incrup(),
	.rdn(rdn),
	.rup(rup),
	.scanout(),
	.serializerenable(wire_sd1a_serializerenable[0:0]),
	.serializerenableout(wire_sd1a_serializerenableout[0:0]),
	.shiftregisterprobe(),
	.terminationclear(aclruser),
	.terminationclock(clock),
	.terminationcontrol(wire_sd1a_terminationcontrol[0:0]),
	.terminationcontrolprobe(),
	.terminationenable(clkenuser)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.otherserializerenable({9{1'b0}}),
	.scanen(1'b0),
	.terminationcontrolin(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		sd1a_0.allow_serial_data_from_core = "false",
		sd1a_0.enable_parallel_termination = "false",
		sd1a_0.power_down = "true",
		sd1a_0.runtime_control = "true",
		sd1a_0.test_mode = "false",
		sd1a_0.lpm_type = "stratixiii_termination";
	assign
		wire_sd1a_serializerenable = serializer_enables[0];
	stratixiii_termination_logic   sd2a_0
	( 
	.parallelloadenable(s2pload),
	.parallelterminationcontrol(wire_sd2a_0parallelterminationcontrol[13:0]),
	.serialloadenable(wire_sd1a_serializerenableout),
	.seriesterminationcontrol(wire_sd2a_0seriesterminationcontrol[13:0]),
	.terminationclock(clock),
	.terminationdata(wire_sd1a_terminationcontrol)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif

	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	assign
		a = {1'b1},
		aclr = 1'b0,
		aclruser = aclruser_dffe,
		cal_shift_busy = cal_shift_busy_t,
		cal_shift_busy_t = cal_shift_busy_dffe,
		calibration_busy = calibration_busy_t,
		calibration_busy_t = (calibration_busy_dffe | calibration_busy_only_dffe),
		calibration_only_req = 1'b0,
		calibration_wait = 1'b0,
		calibration_wait_or = ((calibration_wait[0] | during_shift_only) | during_calibration_only),
		clken = 1'b1,
		clkenuser = clkenuser_dffe,
		during_calibration_only = calibration_busy_only_dffe[0],
		during_shift_only = shift_only_busy_dffe[0],
		parallelterminationcontrol = {wire_sd2a_0parallelterminationcontrol},
		priority_main = (e & a),
		priority_star_or = e[0],
		serializer_enables = {{9{1'b0}}, (serializer_enables_dffe | serializer_only_enables_dffe)},
		seriesterminationcontrol = {wire_sd2a_0seriesterminationcontrol},
		shift_busy = shift_only_busy_dffe,
		shift_only_req = 1'b0,
		state_counter_enable = ((((((((((((~ wire_cntr3_q[2]) & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[0])) & calibration_request[0]) & state_counter_start) | ((((~ wire_cntr3_q[2]) & (~ wire_cntr3_q[1])) & wire_cntr3_q[0]) & (~ calibration_wait_or))) | (((~ wire_cntr3_q[2]) & wire_cntr3_q[1]) & (~ wire_cntr3_q[0]))) | ((((~ wire_cntr3_q[2]) & wire_cntr3_q[1]) & wire_cntr3_q[0]) & wire_cntr5_cout)) | ((wire_cntr3_q[2] & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[0]))) | ((wire_cntr3_q[2] & (~ wire_cntr3_q[1])) & wire_cntr3_q[0])) | (((wire_cntr3_q[2] & wire_cntr3_q[1]) & (~ wire_cntr3_q[0])) & wire_cntr4_cout)) | ((wire_cntr3_q[2] & wire_cntr3_q[1]) & wire_cntr3_q[0])),
		state_counter_start = (~ ((during_shift_only | cal_shift_busy_t[0]) | during_calibration_only)),
		sub_aclruser = {((~ wire_cntr8_q[1]) & wire_cntr8_q[0])},
		sub_clkenuser = {(wire_cntr8_q[1] | wire_cntr8_q[0])},
		sub_state_counter_enable = {(((((((~ wire_cntr8_q[1]) & (~ wire_cntr8_q[0])) & calibration_only_req[0]) & sub_state_counter_start[0]) | ((~ wire_cntr8_q[1]) & wire_cntr8_q[0])) | ((wire_cntr8_q[1] & (~ wire_cntr8_q[0])) & wire_cntr9_cout)) | (wire_cntr8_q[1] & wire_cntr8_q[0]))},
		sub_state_counter_start = (~ (((during_shift_only | cal_shift_busy_t[0]) | calibration_request[0]) | calibration_busy_only_dffe));
endmodule //a_oct_alt_oct_n8n
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module a_oct (
	calibration_request,
	clock,
	rdn,
	rup,
	s2pload,
	cal_shift_busy,
	calibration_busy,
	parallelterminationcontrol,
	seriesterminationcontrol);

	input	[0:0]  calibration_request;
	input	  clock;
	input	[0:0]  rdn;
	input	[0:0]  rup;
	input	[0:0]  s2pload;
	output	[0:0]  cal_shift_busy;
	output	[0:0]  calibration_busy;
	output	[13:0]  parallelterminationcontrol;
	output	[13:0]  seriesterminationcontrol;

	wire [0:0] sub_wire0;
	wire [0:0] sub_wire1;
	wire [13:0] sub_wire2;
	wire [13:0] sub_wire3;
	wire [0:0] calibration_busy = sub_wire0[0:0];
	wire [0:0] cal_shift_busy = sub_wire1[0:0];
	wire [13:0] parallelterminationcontrol = sub_wire2[13:0];
	wire [13:0] seriesterminationcontrol = sub_wire3[13:0];

	a_oct_alt_oct_n8n	a_oct_alt_oct_n8n_component (
				.rdn (rdn),
				.rup (rup),
				.clock (clock),
				.calibration_request (calibration_request),
				.s2pload (s2pload),
				.calibration_busy (sub_wire0),
				.cal_shift_busy (sub_wire1),
				.parallelterminationcontrol (sub_wire2),
				.seriesterminationcontrol (sub_wire3));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: CONSTANT: ENABLE_PARALLEL_TERMINATION STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALT_OCT"
// Retrieval info: CONSTANT: OCT_BLOCK_NUMBER NUMERIC "1"
// Retrieval info: USED_PORT: cal_shift_busy 0 0 1 0 OUTPUT NODEFVAL "cal_shift_busy[0..0]"
// Retrieval info: USED_PORT: calibration_busy 0 0 1 0 OUTPUT NODEFVAL "calibration_busy[0..0]"
// Retrieval info: USED_PORT: calibration_request 0 0 1 0 INPUT NODEFVAL "calibration_request[0..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: parallelterminationcontrol 0 0 14 0 OUTPUT NODEFVAL "parallelterminationcontrol[13..0]"
// Retrieval info: USED_PORT: rdn 0 0 1 0 INPUT NODEFVAL "rdn[0..0]"
// Retrieval info: USED_PORT: rup 0 0 1 0 INPUT NODEFVAL "rup[0..0]"
// Retrieval info: USED_PORT: s2pload 0 0 1 0 INPUT NODEFVAL "s2pload[0..0]"
// Retrieval info: USED_PORT: seriesterminationcontrol 0 0 14 0 OUTPUT NODEFVAL "seriesterminationcontrol[13..0]"
// Retrieval info: CONNECT: cal_shift_busy 0 0 1 0 @cal_shift_busy 0 0 1 0
// Retrieval info: CONNECT: @calibration_request 0 0 1 0 calibration_request 0 0 1 0
// Retrieval info: CONNECT: seriesterminationcontrol 0 0 14 0 @seriesterminationcontrol 0 0 14 0
// Retrieval info: CONNECT: @rup 0 0 1 0 rup 0 0 1 0
// Retrieval info: CONNECT: @s2pload 0 0 1 0 s2pload 0 0 1 0
// Retrieval info: CONNECT: parallelterminationcontrol 0 0 14 0 @parallelterminationcontrol 0 0 14 0
// Retrieval info: CONNECT: calibration_busy 0 0 1 0 @calibration_busy 0 0 1 0
// Retrieval info: CONNECT: @rdn 0 0 1 0 rdn 0 0 1 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL a_oct.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL a_oct.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL a_oct.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL a_oct.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL a_oct_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL a_oct_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf