//exp/microboone/study2011/verify_adc_stream_110207/     feb8,2011
//top file

module  adc_stream_3 (
clk16,clk128,
syncin,runin,trigin,
run0,
clkl,clkr,rxreset,
in0,in1,in2,in3,in4,in5,in6,in7,
align,
alignedleft,alignedright,
lockedleft,lockedright,
//blksync,wrblk,wrch,wrwd,wdsync,wrdat1,wrdat2,
low,blocksize,timesize,
a_channel,a_sample,a_data,a_dav,a_first,a_last,a_block,
b_channel,b_sample,b_data,b_dav,b_first,b_last,
blk_first,blk_last,blocknumber,
wren,addr,dio,
test,
testsample,
testframe,
testchannel,
testph,
testbase,
data
);

//system inputs;
input   clk16;
input   clk128;

input          trigin;    //system trigger
input          syncin;    //system sync
input          runin;     //system run
output         run0;      //run state

input          rxreset;
input          clkl;     //96Mhz clk to left  rx0 t0 rx3
input          clkr;     //96Mhz clk to right rx4 to rx7
input  [8:0]   in0;      //lvds outputs from octal adc0
input  [8:0]   in1;      //lvds outputs from octal adc1
input  [8:0]   in2;      //lvds outputs from octal adc2
input  [8:0]   in3;      //lvds outputs from octal adc3
input  [8:0]   in4;      //lvds outputs from octal adc4
input  [8:0]   in5;      //lvds outputs from octal adc5
input  [8:0]   in6;      //lvds outputs from octal adc6
input  [8:0]   in7;      //lvds outputs from octal adc7

input  [1:0]   test;
input          align;

input          low;       //dc level
input  [11:0]  blocksize; //samples/block
input  [11:0]  timesize;  //drift space

input  [11:0]  testsample;
input  [15:0]  testframe;
input  [5:0]   testchannel;
input  [11:0]  testph;
input  [11:0]  testbase;
input  [15:0]  data;

//rx status:
output         alignedleft;
output         alignedright;
output         lockedleft;
output         lockedright;

//triggered output stream:
output [5:0]   a_channel;
output [13:0]  a_sample;
output [15:0]  a_data;
output         a_dav;
output         a_first;
output         a_last;
output         a_block;

//supernova output stream:
output [5:0]   b_channel;
output [13:0]  b_sample;
output [15:0]  b_data;
output         b_dav;
output         b_first;
output         b_last;
output         blk_first;
output         blk_last;
output [23:0]  blocknumber;

//nbtsram port:
output         wren;      //sram wren low true
output [19:0]  addr;      //sram address
inout  [31:0]  dio;       //sram iodata

wire          alignedleft;
wire          alignedright;
wire          lockedleft;
wire          lockedright;
wire          run0;
wire          blksync;
//wire          wdsync;
wire          phase;
wire  [15:0]  wrdat1;
wire  [15:0]  wrdat2;
wire  [2:0]   wrblk;
wire  [5:0]   wrch;
wire  [10:0]  wrwd;
wire  [15:0]  trigpointer;

//read counters
wire          read;
wire  [2:0]   rdblk;
wire  [10:0]  rdwd;
wire  [5:0]   rdch;
wire  [10:0]  lastwd;

adc_interface_3  adcinterface (
.runin       (runin),
.clk16       (clk16),
.clk128      (clk128),
.syncin      (syncin),
.trigin      (trigin),

.rxreset (rxreset),
.clkl    (clkl),
.clkr    (clkr), 
.in0     (in0),
.in1     (in1),
.in2     (in2),
.in3     (in3),
.in4     (in4),
.in5     (in5),
.in6     (in6),
.in7     (in7),
.align   (align),
.alignedleft  (alignedleft),
.alignedright (alignedright),
.lockedleft   (lockedleft),
.lockedright  (lockedright),
.run0        (run0),
.blksync     (blksync),
//.wdsync      (wdsync),
.phase       (phase),
.wrdat1      (wrdat1),
.wrdat2      (wrdat2),
.wrblk       (wrblk),
.wrch        (wrch),
.wrwd        (wrwd),
.trigpointer (trigpointer),
.low         (low),
.blocksize   (blocksize),
.test        (test),
.testsample  (testsample),
.testframe   (testframe),
.testchannel (testchannel),
.testph      (testph),
.testbase    (testbase),
.data        (data)
);

//sram interface:
wire         wren;          //sram wren
wire [19:0]  addr;          //sram address
wire  [31:0] dio;           //sram iodata
wire [5:0]   a_channel;
wire [13:0]  a_sample;
wire [15:0]  a_data;
wire         a_dav;
wire         a_first;
wire         a_last;
wire         a_block;
wire [5:0]   b_channel;
wire [13:0]  b_sample;
wire [15:0]  b_data;
wire         b_dav;
wire         b_first;
wire         b_last;
wire         blk_first;
wire         blk_last;
wire [23:0]  blocknumber;

//ram_framed_rdwr output_stream (
ram_framed_3  output_stream (
//inputs:
.clk         (clk128),
.run0        (run0),
.blksync     (blksync),
.phase       (phase),
.wrdat1      (wrdat1),
.wrdat2      (wrdat2),
.wrblk       (wrblk),
.wrwd        (wrwd),
.wrch        (wrch),
.trigpointer (trigpointer),
//nbtram port:
.wren        (wren),   //sram wren low true
.addr        (addr),   //sram address
.dio         (dio),    //sram iodata
//outputs:
.timesize    (timesize),
.a_channel   (a_channel),
.a_sample    (a_sample),
.a_data      (a_data),
.a_dav       (a_dav),
.a_first     (a_first),
.a_last      (a_last),
.a_block     (a_block),
.b_channel   (b_channel),
.b_sample    (b_sample),
.b_data      (b_data),
.b_dav       (b_dav),
.b_first     (b_first),
.b_last      (b_last),
.blk_first   (blk_first),
.blk_last    (blk_last),
.blocknumber (blocknumber)
);

endmodule