//exp/microboone/adc_interface/ april1,2011

module  adcsync (
outclock,clk16,rx_locked,alsync,load,adc,
out,alvalid
);

input         outclock;
input         clk16;
input         rx_locked;
input         alsync;
input         load;
input  [95:0] adc;
output [95:0] out;
output        alvalid;

//synchronize to clk16:
reg          wren;
reg          udel;
reg          alval;

always @ (posedge outclock)
begin   
   if       (rx_locked & load & !alsync)     wren <= 1'b1;
   else                            wren <= 1'b0;
   
                                   udel <= wren; 
                                   
   if       (wren | udel)         alval <= 1'b1;
   else                           alval <= 1'b0; 
end

reg     alvalid;
always @ (posedge clk16)
begin
      alvalid <= alval;
end


reg  [1:0]  g;
reg         r0,r1;
reg  [1:0]  rdadd;
wire [95:0] out;

always @ (posedge outclock)
begin
     if      (load & (g==2'b00)) g <= 2'b01;
     else if (load & (g==2'b01)) g <= 2'b11;
     else if (load & (g==2'b11)) g <= 2'b10;
     else if (load & (g==2'b10)) g <= 2'b00;      
end

always @ (posedge clk16)
begin
         r0 <= g[0];
         r1 <= g[1];
 rdadd[1:0] <= {r1,r0};
end

dp4x96  dp (
.wrclock    (outclock),
.rdclock    (clk16),
.wren       (wren),
.data       (adc),
.wraddress  (g),
.rdaddress  (rdadd),
.q          (out)
);

endmodule