// megafunction wizard: %PARALLEL_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: parallel_add 

// ============================================================
// File Name: add15x1.v
// Megafunction Name(s):
// 			parallel_add
//
// Simulation Library Files(s):
// 			altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module add15x1 (
	clock,
	data0x,
	data10x,
	data11x,
	data12x,
	data13x,
	data14x,
	data1x,
	data2x,
	data3x,
	data4x,
	data5x,
	data6x,
	data7x,
	data8x,
	data9x,
	result);

	input	  clock;
	input	[0:0]  data0x;
	input	[0:0]  data10x;
	input	[0:0]  data11x;
	input	[0:0]  data12x;
	input	[0:0]  data13x;
	input	[0:0]  data14x;
	input	[0:0]  data1x;
	input	[0:0]  data2x;
	input	[0:0]  data3x;
	input	[0:0]  data4x;
	input	[0:0]  data5x;
	input	[0:0]  data6x;
	input	[0:0]  data7x;
	input	[0:0]  data8x;
	input	[0:0]  data9x;
	output	[4:0]  result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0	  clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire [4:0] sub_wire0;
	wire [0:0] sub_wire16 = data14x[0:0];
	wire [0:0] sub_wire15 = data12x[0:0];
	wire [0:0] sub_wire14 = data6x[0:0];
	wire [0:0] sub_wire13 = data5x[0:0];
	wire [0:0] sub_wire12 = data10x[0:0];
	wire [0:0] sub_wire11 = data4x[0:0];
	wire [0:0] sub_wire10 = data3x[0:0];
	wire [0:0] sub_wire9 = data2x[0:0];
	wire [0:0] sub_wire8 = data1x[0:0];
	wire [0:0] sub_wire7 = data0x[0:0];
	wire [0:0] sub_wire6 = data9x[0:0];
	wire [0:0] sub_wire5 = data8x[0:0];
	wire [0:0] sub_wire4 = data11x[0:0];
	wire [0:0] sub_wire3 = data7x[0:0];
	wire [4:0] result = sub_wire0[4:0];
	wire [0:0] sub_wire1 = data13x[0:0];
	wire [14:0] sub_wire2 = {sub_wire16, sub_wire1, sub_wire15, sub_wire4, sub_wire12, sub_wire6, sub_wire5, sub_wire3, sub_wire14, sub_wire13, sub_wire11, sub_wire10, sub_wire9, sub_wire8, sub_wire7};

	parallel_add	parallel_add_component (
				.clock (clock),
				.data (sub_wire2),
				.result (sub_wire0)
				// synopsys translate_off
				,
				.aclr (),
				.clken ()
				// synopsys translate_on
				);
	defparam
		parallel_add_component.msw_subtract = "NO",
		parallel_add_component.pipeline = 1,
		parallel_add_component.representation = "UNSIGNED",
		parallel_add_component.result_alignment = "LSB",
		parallel_add_component.shift = 0,
		parallel_add_component.size = 15,
		parallel_add_component.width = 1,
		parallel_add_component.widthr = 5;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: MSW_SUBTRACT STRING "NO"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: RESULT_ALIGNMENT STRING "LSB"
// Retrieval info: CONSTANT: SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: SIZE NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: WIDTHR NUMERIC "5"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND "clock"
// Retrieval info: USED_PORT: data0x 0 0 1 0 INPUT NODEFVAL "data0x[0..0]"
// Retrieval info: USED_PORT: data10x 0 0 1 0 INPUT NODEFVAL "data10x[0..0]"
// Retrieval info: USED_PORT: data11x 0 0 1 0 INPUT NODEFVAL "data11x[0..0]"
// Retrieval info: USED_PORT: data12x 0 0 1 0 INPUT NODEFVAL "data12x[0..0]"
// Retrieval info: USED_PORT: data13x 0 0 1 0 INPUT NODEFVAL "data13x[0..0]"
// Retrieval info: USED_PORT: data14x 0 0 1 0 INPUT NODEFVAL "data14x[0..0]"
// Retrieval info: USED_PORT: data1x 0 0 1 0 INPUT NODEFVAL "data1x[0..0]"
// Retrieval info: USED_PORT: data2x 0 0 1 0 INPUT NODEFVAL "data2x[0..0]"
// Retrieval info: USED_PORT: data3x 0 0 1 0 INPUT NODEFVAL "data3x[0..0]"
// Retrieval info: USED_PORT: data4x 0 0 1 0 INPUT NODEFVAL "data4x[0..0]"
// Retrieval info: USED_PORT: data5x 0 0 1 0 INPUT NODEFVAL "data5x[0..0]"
// Retrieval info: USED_PORT: data6x 0 0 1 0 INPUT NODEFVAL "data6x[0..0]"
// Retrieval info: USED_PORT: data7x 0 0 1 0 INPUT NODEFVAL "data7x[0..0]"
// Retrieval info: USED_PORT: data8x 0 0 1 0 INPUT NODEFVAL "data8x[0..0]"
// Retrieval info: USED_PORT: data9x 0 0 1 0 INPUT NODEFVAL "data9x[0..0]"
// Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL "result[4..0]"
// Retrieval info: CONNECT: @data 0 0 1 12 data12x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 6 data6x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 11 data11x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 5 data5x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 10 data10x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 4 data4x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 3 data3x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 2 data2x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 1 data1x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 0 data0x 0 0 1 0
// Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 9 data9x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 14 data14x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 8 data8x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 13 data13x 0 0 1 0
// Retrieval info: CONNECT: @data 0 0 1 7 data7x 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL add15x1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL add15x1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add15x1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add15x1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL add15x1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add15x1_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf