Hierarchy | Input | Constant Input | Unused Input | Floating Input | Output | Constant Output | Unused Output | Floating Output | Bidir | Constant Bidir | Unused Bidir | Input only Bidir | Output only Bidir
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
hist_silo|fifo1|dcfifo_component|auto_generated|wrfull_eq_comp | 24 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|rdempty_eq_comp | 24 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 | 14 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|ws_dgrp | 14 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe13 | 14 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|rs_dgwp | 14 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|rs_bwp | 14 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|rs_brp | 14 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|fifo_ram | 60 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin | 12 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin | 12 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1|dcfifo_component|auto_generated | 37 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo|fifo1 | 37 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
hist_silo | 53 | 0 | 16 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
rdbk_status | 86 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
rdbk_counters | 146 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|encoder|hammingcode_altecc_encoder_c0c_component | 25 | 0 | 0 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|encoder | 25 | 0 | 0 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo|scfifo_component|auto_generated|dpfifo|wr_ptr | 3 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo|scfifo_component|auto_generated|dpfifo|usedw_counter | 4 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_msb | 3 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo|scfifo_component|auto_generated|dpfifo|three_comparison | 16 | 8 | 0 | 8 | 1 | 8 | 8 | 8 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo|scfifo_component|auto_generated|dpfifo|almost_full_comparer | 16 | 8 | 0 | 8 | 1 | 8 | 8 | 8 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo|scfifo_component|auto_generated|dpfifo|FIFOram | 38 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo|scfifo_component|auto_generated|dpfifo | 22 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo|scfifo_component|auto_generated | 21 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24|fifo | 21 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|gear16_24 | 21 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe15 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|ws_dgrp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rs_dgwp | 12 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|fifo_ram | 41 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo|dcfifo_component|auto_generated | 23 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen|fifo | 23 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
datagen | 22 | 2 | 0 | 2 | 36 | 2 | 2 | 2 | 0 | 0 | 0 | 0 | 0
slow | 11 | 0 | 0 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|state_mc_decode|auto_generated | 3 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|state_mc_counter|auto_generated | 3 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|state_mc_cmpr|auto_generated | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|rd_data_output_cmpr|auto_generated | 12 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|pre_amble_cmpr|auto_generated | 12 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio | 47 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig|recon_alt2gxb_reconfig_tfm_component|calibration|alt_cal_mux_gen.testbus_mux|auto_generated | 9 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig|recon_alt2gxb_reconfig_tfm_component | 18 | 0 | 8 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|reconfig | 18 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|transrec|xmitrec_alt4gxb_tv9a_component | 48 | 8 | 0 | 8 | 75 | 8 | 8 | 8 | 0 | 0 | 0 | 0 | 0
transmit_2|transrec | 48 | 0 | 0 | 0 | 65 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe18 | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|ws_dgrp | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|ws_bwp | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|ws_brp | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe14 | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rs_dgwp | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|fifo_ram|mux13 | 138 | 0 | 0 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|fifo_ram|wren_decode_a | 3 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|fifo_ram|rden_decode_b | 2 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|fifo_ram|decode12 | 3 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|fifo_ram | 69 | 0 | 0 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin | 16 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin | 16 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo|dcfifo_component|auto_generated | 39 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|xmitfifo | 39 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|gear16_32 | 21 | 0 | 0 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe15 | 10 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|ws_dgrp | 10 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 | 10 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rs_dgwp | 10 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|fifo_ram | 75 | 0 | 0 | 0 | 55 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|wrptr_g1p | 2 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated|rdptr_g1p | 2 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo|dcfifo_component|auto_generated | 59 | 0 | 0 | 0 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16|fifo | 59 | 0 | 0 | 0 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|stream16 | 30 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hamming|decode24_altecc_decoder_lff_component|error_bit_decoder|auto_generated | 5 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hamming|decode24_altecc_decoder_lff_component | 31 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hamming | 31 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe15 | 11 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|ws_dgrp | 11 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 | 11 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rs_dgwp | 11 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|fifo_ram | 39 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo|dcfifo_component|auto_generated | 23 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2|hedfifo | 23 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_2 | 46 | 0 | 2 | 0 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|state_mc_decode|auto_generated | 3 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|state_mc_counter|auto_generated | 3 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|state_mc_cmpr|auto_generated | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|rd_data_output_cmpr|auto_generated | 12 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio|pre_amble_cmpr|auto_generated | 12 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig|recon_alt2gxb_reconfig_tfm_component|dprio | 47 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig|recon_alt2gxb_reconfig_tfm_component|calibration|alt_cal_mux_gen.testbus_mux|auto_generated | 9 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig|recon_alt2gxb_reconfig_tfm_component | 18 | 0 | 8 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|reconfig | 18 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|transrec|xmitrec_alt4gxb_tv9a_component | 48 | 8 | 0 | 8 | 75 | 8 | 8 | 8 | 0 | 0 | 0 | 0 | 0
transmit_1|transrec | 48 | 0 | 0 | 0 | 65 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe18 | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|ws_dgrp | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|ws_bwp | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|ws_brp | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe14 | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rs_dgwp | 18 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|fifo_ram|mux13 | 138 | 0 | 0 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|fifo_ram|wren_decode_a | 3 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|fifo_ram|rden_decode_b | 2 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|fifo_ram|decode12 | 3 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|fifo_ram | 69 | 0 | 0 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin | 16 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin | 16 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo|dcfifo_component|auto_generated | 39 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|xmitfifo | 39 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|gear16_32 | 21 | 0 | 0 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe15 | 10 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|ws_dgrp | 10 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 | 10 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rs_dgwp | 10 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|fifo_ram | 75 | 0 | 0 | 0 | 55 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|wrptr_g1p | 2 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated|rdptr_g1p | 2 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo|dcfifo_component|auto_generated | 59 | 0 | 0 | 0 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16|fifo | 59 | 0 | 0 | 0 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|stream16 | 30 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hamming|decode24_altecc_decoder_lff_component|error_bit_decoder|auto_generated | 5 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hamming|decode24_altecc_decoder_lff_component | 31 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hamming | 31 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rdempty_eq_comp_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rdempty_eq_comp_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_msb | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe15 | 11 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|ws_dgrp | 11 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 | 11 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rs_dgwp | 11 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|fifo_ram | 39 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|wrptr_g1p | 3 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated|rdptr_g1p | 3 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo|dcfifo_component|auto_generated | 23 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1|hedfifo | 23 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
transmit_1 | 46 | 0 | 2 | 0 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
synchronizer|dpram|altsyncram_component|auto_generated | 45 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
synchronizer|dpram | 45 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
synchronizer | 39 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|rx_outclock_buf | 4 | 3 | 0 | 3 | 1 | 3 | 3 | 3 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum83a | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum62a | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum41a | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum20a | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum188a | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum167a | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum146a | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum125a | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated|lock_cnt_accum104a | 6 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link|ALTLVDS_RX_component|auto_generated | 38 | 0 | 0 | 0 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
link | 38 | 0 | 0 | 0 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
align | 40 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
clocks|altpll_component|auto_generated | 2 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
clocks | 1 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0