//altlvds_rx BUFFER_IMPLEMENTATION="RAM" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" COMMON_RX_TX_PLL="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DATA_ALIGN_ROLLOVER=4 DATA_RATE="512.0 Mbps" DESERIALIZATION_FACTOR=4 DEVICE_FAMILY="Arria II GX" DPA_INITIAL_PHASE_VALUE=0 DPLL_LOCK_COUNT=0 DPLL_LOCK_WINDOW=0 ENABLE_DPA_ALIGN_TO_RISING_EDGE_ONLY="OFF" ENABLE_DPA_CALIBRATION="ON" ENABLE_DPA_INITIAL_PHASE_SELECTION="ON" ENABLE_DPA_MODE="ON" ENABLE_DPA_PLL_CALIBRATION="OFF" ENABLE_SOFT_CDR_MODE="OFF" IMPLEMENT_IN_LES="OFF" INCLOCK_BOOST=0 INCLOCK_DATA_ALIGNMENT="EDGE_ALIGNED" INCLOCK_PERIOD=7812 INCLOCK_PHASE_SHIFT=1953 INPUT_DATA_RATE=512 NUMBER_OF_CHANNELS=9 OUTCLOCK_RESOURCE="AUTO" PORT_RX_CHANNEL_DATA_ALIGN="PORT_USED" PORT_RX_DATA_ALIGN="PORT_UNUSED" REGISTERED_OUTPUT="ON" SIM_DPA_IS_NEGATIVE_PPM_DRIFT="OFF" SIM_DPA_NET_PPM_VARIATION=0 SIM_DPA_OUTPUT_CLOCK_PHASE_SHIFT=0 USE_CORECLOCK_INPUT="OFF" USE_DPLL_RAWPERROR="OFF" USE_EXTERNAL_PLL="OFF" USE_NO_PHASE_SHIFT="ON" X_ON_BITSLIP="ON" pll_areset rx_channel_data_align rx_dpa_locked rx_fifo_reset rx_in rx_inclock rx_locked rx_out rx_outclock rx_reset ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 11.1SP2 cbx_altaccumulate 2012:01:25:21:14:55:SJ cbx_altclkbuf 2012:01:25:21:14:55:SJ cbx_altddio_in 2012:01:25:21:14:55:SJ cbx_altddio_out 2012:01:25:21:14:55:SJ cbx_altiobuf_bidir 2012:01:25:21:14:55:SJ cbx_altiobuf_in 2012:01:25:21:14:55:SJ cbx_altiobuf_out 2012:01:25:21:14:55:SJ cbx_altlvds_rx 2012:01:25:21:14:55:SJ cbx_altpll 2012:01:25:21:14:56:SJ cbx_altsyncram 2012:01:25:21:14:56:SJ cbx_arriav 2012:01:25:21:14:54:SJ cbx_cyclone 2012:01:25:21:14:56:SJ cbx_cycloneii 2012:01:25:21:14:56:SJ cbx_lpm_add_sub 2012:01:25:21:14:56:SJ cbx_lpm_compare 2012:01:25:21:14:56:SJ cbx_lpm_counter 2012:01:25:21:14:56:SJ cbx_lpm_decode 2012:01:25:21:14:56:SJ cbx_lpm_mux 2012:01:25:21:14:56:SJ cbx_lpm_shiftreg 2012:01:25:21:14:56:SJ cbx_maxii 2012:01:25:21:14:56:SJ cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratix 2012:01:25:21:14:56:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_stratixiii 2012:01:25:21:14:56:SJ cbx_stratixv 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END
//CBXI_INSTANCE_NAME="readcontrol_linki_v10_link_altlvds_rx_ALTLVDS_RX_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2011 Altera Corporation
//  Your use of Altera Corporation's design tools, logic functions 
//  and other software and tools, and its AMPP partner logic 
//  functions, and any output files from any of the foregoing 
//  (including device programming or simulation files), and any 
//  associated documentation or information are expressly subject 
//  to the terms and conditions of the Altera Program License 
//  Subscription Agreement, Altera MegaCore Function License 
//  Agreement, or other applicable license agreement, including, 
//  without limitation, that your use is for the sole purpose of 
//  programming logic devices manufactured by Altera and sold by 
//  Altera or its authorized distributors.  Please refer to the 
//  applicable agreement for further details.




//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=2 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//adder CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH=3 dataa datab datac result
//VERSION_BEGIN 11.1SP2 cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_util_mgl 2012:01:25:21:14:56:SJ  VERSION_END


//altaccumulate CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Arria II GX" WIDTH_IN=3 WIDTH_OUT=8 aclr clken clock cout data
//VERSION_BEGIN 11.1SP2 cbx_altaccumulate 2012:01:25:21:14:55:SJ cbx_cycloneii 2012:01:25:21:14:56:SJ cbx_lpm_add_sub 2012:01:25:21:14:56:SJ cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratix 2012:01:25:21:14:56:SJ cbx_stratixii 2012:01:25:21:14:56:SJ  VERSION_END

//synthesis_resources = lut 8 reg 8 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  linki_v10_accum
	( 
	aclr,
	clken,
	clock,
	cout,
	data,
	result) /* synthesis synthesis_clearbox=1 */;
	input   aclr;
	input   clken;
	input   clock;
	output   cout;
	input   [2:0]  data;
	output   [7:0]  result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   aclr;
	tri1   clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	reg	[7:0]	acc_ffa;
	wire  [0:0]   wire_acc_cella_0cout;
	wire  [0:0]   wire_acc_cella_1cout;
	wire  [0:0]   wire_acc_cella_2cout;
	wire  [0:0]   wire_acc_cella_3cout;
	wire  [0:0]   wire_acc_cella_4cout;
	wire  [0:0]   wire_acc_cella_5cout;
	wire  [0:0]   wire_acc_cella_6cout;
	wire  [0:0]   wire_acc_cella_7cout;
	wire  [7:0]   wire_acc_cella_dataa;
	wire  [7:0]   wire_acc_cella_datab;
	wire  [7:0]   wire_acc_cella_sumout;
	wire sload;

	// synopsys translate_off
	initial
		acc_ffa = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) acc_ffa <= 8'b0;
		else if  (clken == 1'b1)   acc_ffa <= wire_acc_cella_sumout;
	arriaii_lcell_comb   acc_cella_0
	( 
	.cin(1'b0),
	.combout(),
	.cout(wire_acc_cella_0cout[0:0]),
	.dataa(wire_acc_cella_dataa[0:0]),
	.datab(wire_acc_cella_datab[0:0]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[0:0]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_0.lut_mask = 64'h000033330000AAAA,
		acc_cella_0.lpm_type = "arriaii_lcell_comb";
	arriaii_lcell_comb   acc_cella_1
	( 
	.cin(wire_acc_cella_0cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_1cout[0:0]),
	.dataa(wire_acc_cella_dataa[1:1]),
	.datab(wire_acc_cella_datab[1:1]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[1:1]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_1.lut_mask = 64'h000033330000AAAA,
		acc_cella_1.lpm_type = "arriaii_lcell_comb";
	arriaii_lcell_comb   acc_cella_2
	( 
	.cin(wire_acc_cella_1cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_2cout[0:0]),
	.dataa(wire_acc_cella_dataa[2:2]),
	.datab(wire_acc_cella_datab[2:2]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[2:2]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_2.lut_mask = 64'h000033330000AAAA,
		acc_cella_2.lpm_type = "arriaii_lcell_comb";
	arriaii_lcell_comb   acc_cella_3
	( 
	.cin(wire_acc_cella_2cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_3cout[0:0]),
	.dataa(wire_acc_cella_dataa[3:3]),
	.datab(wire_acc_cella_datab[3:3]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[3:3]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_3.lut_mask = 64'h000033330000AAAA,
		acc_cella_3.lpm_type = "arriaii_lcell_comb";
	arriaii_lcell_comb   acc_cella_4
	( 
	.cin(wire_acc_cella_3cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_4cout[0:0]),
	.dataa(wire_acc_cella_dataa[4:4]),
	.datab(wire_acc_cella_datab[4:4]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[4:4]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_4.lut_mask = 64'h000033330000AAAA,
		acc_cella_4.lpm_type = "arriaii_lcell_comb";
	arriaii_lcell_comb   acc_cella_5
	( 
	.cin(wire_acc_cella_4cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_5cout[0:0]),
	.dataa(wire_acc_cella_dataa[5:5]),
	.datab(wire_acc_cella_datab[5:5]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[5:5]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_5.lut_mask = 64'h000033330000AAAA,
		acc_cella_5.lpm_type = "arriaii_lcell_comb";
	arriaii_lcell_comb   acc_cella_6
	( 
	.cin(wire_acc_cella_5cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_6cout[0:0]),
	.dataa(wire_acc_cella_dataa[6:6]),
	.datab(wire_acc_cella_datab[6:6]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[6:6]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_6.lut_mask = 64'h000033330000AAAA,
		acc_cella_6.lpm_type = "arriaii_lcell_comb";
	arriaii_lcell_comb   acc_cella_7
	( 
	.cin(wire_acc_cella_6cout[0:0]),
	.combout(),
	.cout(wire_acc_cella_7cout[0:0]),
	.dataa(wire_acc_cella_dataa[7:7]),
	.datab(wire_acc_cella_datab[7:7]),
	.shareout(),
	.sumout(wire_acc_cella_sumout[7:7]),
	.datac(1'b0),
	.datad(1'b0),
	.datae(1'b0),
	.dataf(1'b0),
	.datag(1'b0),
	.sharein(1'b0)
	);
	defparam
		acc_cella_7.lut_mask = 64'h000033330000AAAA,
		acc_cella_7.lpm_type = "arriaii_lcell_comb";
	assign
		wire_acc_cella_dataa = acc_ffa,
		wire_acc_cella_datab = {{5{1'b0}}, data};
	assign
		cout = ((~ sload) & wire_acc_cella_7cout[0:0]),
		result = acc_ffa,
		sload = 1'b0;
endmodule //linki_v10_accum


//altclkctrl CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_TYPE="AUTO" DEVICE_FAMILY="Arria II GX" inclk outclk
//VERSION_BEGIN 11.1SP2 cbx_altclkbuf 2012:01:25:21:14:55:SJ cbx_cycloneii 2012:01:25:21:14:56:SJ cbx_lpm_add_sub 2012:01:25:21:14:56:SJ cbx_lpm_compare 2012:01:25:21:14:56:SJ cbx_lpm_decode 2012:01:25:21:14:56:SJ cbx_lpm_mux 2012:01:25:21:14:56:SJ cbx_mgl 2012:01:25:21:17:49:SJ cbx_stratix 2012:01:25:21:14:56:SJ cbx_stratixii 2012:01:25:21:14:56:SJ cbx_stratixiii 2012:01:25:21:14:56:SJ cbx_stratixv 2012:01:25:21:14:56:SJ  VERSION_END

//synthesis_resources = clkctrl 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  linki_v10_altclkctrl
	( 
	inclk,
	outclk) /* synthesis synthesis_clearbox=1 */;
	input   [3:0]  inclk;
	output   outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   [3:0]  inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire  wire_sd210_outclk;
	wire [1:0]  clkselect;
	wire ena;

	arriaii_clkena   sd210
	( 
	.ena(ena),
	.enaout(),
	.inclk(inclk[0]),
	.outclk(wire_sd210_outclk)
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		sd210.clock_type = "AUTO",
		sd210.ena_register_mode = "falling edge",
		sd210.lpm_type = "arriaii_clkena";
	assign
		clkselect = {2{1'b0}},
		ena = 1'b1,
		outclk = wire_sd210_outclk;
endmodule //linki_v10_altclkctrl

//synthesis_resources = arriaii_lvds_receiver 9 arriaii_pll 1 clkctrl 1 lut 162 reg 253 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SUPPRESS_DA_RULE_INTERNAL=C104;{-to pll} AUTO_MERGE_PLLS=OFF;-name SOURCE_MULTICYCLE 4 -from wire_rx_dataout* -to rxreg*;-name SOURCE_MULTICYCLE_HOLD 4 -from wire_rx_dataout* -to rxreg*"} *)
module  linki_v10_lvds_rx
	( 
	pll_areset,
	rx_channel_data_align,
	rx_dpa_locked,
	rx_fifo_reset,
	rx_in,
	rx_inclock,
	rx_locked,
	rx_out,
	rx_outclock,
	rx_reset) /* synthesis synthesis_clearbox=1 */;
	input   pll_areset;
	input   [8:0]  rx_channel_data_align;
	output   [8:0]  rx_dpa_locked;
	input   [8:0]  rx_fifo_reset;
	input   [8:0]  rx_in;
	input   rx_inclock;
	output   rx_locked;
	output   [35:0]  rx_out;
	output   rx_outclock;
	input   [8:0]  rx_reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   pll_areset;
	tri0   [8:0]  rx_channel_data_align;
	tri0   [8:0]  rx_fifo_reset;
	tri0   [8:0]  rx_reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire	[1:0]	wire_add10_result;
	wire	[1:0]	wire_add115_result;
	wire	[2:0]	wire_add120_result;
	wire	[1:0]	wire_add136_result;
	wire	[2:0]	wire_add141_result;
	wire	[2:0]	wire_add15_result;
	wire	[1:0]	wire_add157_result;
	wire	[2:0]	wire_add162_result;
	wire	[1:0]	wire_add178_result;
	wire	[2:0]	wire_add183_result;
	wire	[1:0]	wire_add31_result;
	wire	[2:0]	wire_add36_result;
	wire	[1:0]	wire_add52_result;
	wire	[2:0]	wire_add57_result;
	wire	[1:0]	wire_add73_result;
	wire	[2:0]	wire_add78_result;
	wire	[1:0]	wire_add94_result;
	wire	[2:0]	wire_add99_result;
	wire  wire_lock_cnt_accum104a_cout;
	wire  [7:0]   wire_lock_cnt_accum104a_result;
	wire  wire_lock_cnt_accum125a_cout;
	wire  wire_lock_cnt_accum146a_cout;
	wire  wire_lock_cnt_accum167a_cout;
	wire  wire_lock_cnt_accum188a_cout;
	wire  wire_lock_cnt_accum20a_cout;
	wire  wire_lock_cnt_accum41a_cout;
	wire  wire_lock_cnt_accum62a_cout;
	wire  wire_lock_cnt_accum83a_cout;
	wire  wire_rx_outclock_buf_outclk;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe108;
	wire	wire_dffe108_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe109;
	wire	wire_dffe109_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe110;
	wire	wire_dffe110_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe111;
	wire	wire_dffe111_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe112;
	wire	wire_dffe112_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe113;
	wire	wire_dffe113_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe114;
	wire	wire_dffe114_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe129;
	wire	wire_dffe129_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe130;
	wire	wire_dffe130_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe131;
	wire	wire_dffe131_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe132;
	wire	wire_dffe132_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe133;
	wire	wire_dffe133_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe134;
	wire	wire_dffe134_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe135;
	wire	wire_dffe135_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe150;
	wire	wire_dffe150_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe151;
	wire	wire_dffe151_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe152;
	wire	wire_dffe152_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe153;
	wire	wire_dffe153_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe154;
	wire	wire_dffe154_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe155;
	wire	wire_dffe155_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe156;
	wire	wire_dffe156_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe171;
	wire	wire_dffe171_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe172;
	wire	wire_dffe172_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe173;
	wire	wire_dffe173_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe174;
	wire	wire_dffe174_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe175;
	wire	wire_dffe175_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe176;
	wire	wire_dffe176_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe177;
	wire	wire_dffe177_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe24;
	wire	wire_dffe24_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe25;
	wire	wire_dffe25_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe26;
	wire	wire_dffe26_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe27;
	wire	wire_dffe27_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe28;
	wire	wire_dffe28_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe29;
	wire	wire_dffe29_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe3;
	wire	wire_dffe3_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe30;
	wire	wire_dffe30_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe4;
	wire	wire_dffe4_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe45;
	wire	wire_dffe45_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe46;
	wire	wire_dffe46_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe47;
	wire	wire_dffe47_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe48;
	wire	wire_dffe48_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe49;
	wire	wire_dffe49_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe5;
	wire	wire_dffe5_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe50;
	wire	wire_dffe50_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe51;
	wire	wire_dffe51_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe6;
	wire	wire_dffe6_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe66;
	wire	wire_dffe66_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe67;
	wire	wire_dffe67_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe68;
	wire	wire_dffe68_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe69;
	wire	wire_dffe69_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe7;
	wire	wire_dffe7_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe70;
	wire	wire_dffe70_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe71;
	wire	wire_dffe71_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe72;
	wire	wire_dffe72_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe8;
	wire	wire_dffe8_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe87;
	wire	wire_dffe87_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe88;
	wire	wire_dffe88_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe89;
	wire	wire_dffe89_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe9;
	wire	wire_dffe9_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe90;
	wire	wire_dffe90_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe91;
	wire	wire_dffe91_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe92;
	wire	wire_dffe92_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	dffe93;
	wire	wire_dffe93_clrn;
	reg	extra_reg107a;
	wire	wire_extra_reg107a_clrn;
	reg	extra_reg128a;
	wire	wire_extra_reg128a_clrn;
	reg	extra_reg149a;
	wire	wire_extra_reg149a_clrn;
	reg	extra_reg170a;
	wire	wire_extra_reg170a_clrn;
	reg	extra_reg23a;
	wire	wire_extra_reg23a_clrn;
	reg	extra_reg2a;
	wire	wire_extra_reg2a_clrn;
	reg	extra_reg44a;
	wire	wire_extra_reg44a_clrn;
	reg	extra_reg65a;
	wire	wire_extra_reg65a_clrn;
	reg	extra_reg86a;
	wire	wire_extra_reg86a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg105a;
	wire	wire_lock_out_reg105a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg126a;
	wire	wire_lock_out_reg126a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg147a;
	wire	wire_lock_out_reg147a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg168a;
	wire	wire_lock_out_reg168a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg189a;
	wire	wire_lock_out_reg189a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg21a;
	wire	wire_lock_out_reg21a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg42a;
	wire	wire_lock_out_reg42a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg63a;
	wire	wire_lock_out_reg63a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg84a;
	wire	wire_lock_out_reg84a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly191a;
	wire	wire_lock_out_reg_dly191a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly193a;
	wire	wire_lock_out_reg_dly193a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly195a;
	wire	wire_lock_out_reg_dly195a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly197a;
	wire	wire_lock_out_reg_dly197a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly199a;
	wire	wire_lock_out_reg_dly199a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly201a;
	wire	wire_lock_out_reg_dly201a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly203a;
	wire	wire_lock_out_reg_dly203a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly205a;
	wire	wire_lock_out_reg_dly205a_clrn;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	lock_out_reg_dly207a;
	wire	wire_lock_out_reg_dly207a_clrn;
	wire	[1:0]	wire_lock_state_mc190a_d;
	reg	[1:0]	lock_state_mc190a;
	wire	[1:0]	wire_lock_state_mc190a_clrn;
	wire	[1:0]	wire_lock_state_mc190a_ena;
	wire	[1:0]	wire_lock_state_mc192a_d;
	reg	[1:0]	lock_state_mc192a;
	wire	[1:0]	wire_lock_state_mc192a_clrn;
	wire	[1:0]	wire_lock_state_mc192a_ena;
	wire	[1:0]	wire_lock_state_mc194a_d;
	reg	[1:0]	lock_state_mc194a;
	wire	[1:0]	wire_lock_state_mc194a_clrn;
	wire	[1:0]	wire_lock_state_mc194a_ena;
	wire	[1:0]	wire_lock_state_mc196a_d;
	reg	[1:0]	lock_state_mc196a;
	wire	[1:0]	wire_lock_state_mc196a_clrn;
	wire	[1:0]	wire_lock_state_mc196a_ena;
	wire	[1:0]	wire_lock_state_mc198a_d;
	reg	[1:0]	lock_state_mc198a;
	wire	[1:0]	wire_lock_state_mc198a_clrn;
	wire	[1:0]	wire_lock_state_mc198a_ena;
	wire	[1:0]	wire_lock_state_mc200a_d;
	reg	[1:0]	lock_state_mc200a;
	wire	[1:0]	wire_lock_state_mc200a_clrn;
	wire	[1:0]	wire_lock_state_mc200a_ena;
	wire	[1:0]	wire_lock_state_mc202a_d;
	reg	[1:0]	lock_state_mc202a;
	wire	[1:0]	wire_lock_state_mc202a_clrn;
	wire	[1:0]	wire_lock_state_mc202a_ena;
	wire	[1:0]	wire_lock_state_mc204a_d;
	reg	[1:0]	lock_state_mc204a;
	wire	[1:0]	wire_lock_state_mc204a_clrn;
	wire	[1:0]	wire_lock_state_mc204a_ena;
	wire	[1:0]	wire_lock_state_mc206a_d;
	reg	[1:0]	lock_state_mc206a;
	wire	[1:0]	wire_lock_state_mc206a_clrn;
	wire	[1:0]	wire_lock_state_mc206a_ena;
	wire	[3:0]	wire_pad_regr106a_d;
	reg	[3:0]	pad_regr106a;
	wire	[3:0]	wire_pad_regr106a_clrn;
	wire	[3:0]	wire_pad_regr127a_d;
	reg	[3:0]	pad_regr127a;
	wire	[3:0]	wire_pad_regr127a_clrn;
	wire	[3:0]	wire_pad_regr148a_d;
	reg	[3:0]	pad_regr148a;
	wire	[3:0]	wire_pad_regr148a_clrn;
	wire	[3:0]	wire_pad_regr169a_d;
	reg	[3:0]	pad_regr169a;
	wire	[3:0]	wire_pad_regr169a_clrn;
	wire	[3:0]	wire_pad_regr1a_d;
	reg	[3:0]	pad_regr1a;
	wire	[3:0]	wire_pad_regr1a_clrn;
	wire	[3:0]	wire_pad_regr22a_d;
	reg	[3:0]	pad_regr22a;
	wire	[3:0]	wire_pad_regr22a_clrn;
	wire	[3:0]	wire_pad_regr43a_d;
	reg	[3:0]	pad_regr43a;
	wire	[3:0]	wire_pad_regr43a_clrn;
	wire	[3:0]	wire_pad_regr64a_d;
	reg	[3:0]	pad_regr64a;
	wire	[3:0]	wire_pad_regr64a_clrn;
	wire	[3:0]	wire_pad_regr85a_d;
	reg	[3:0]	pad_regr85a;
	wire	[3:0]	wire_pad_regr85a_clrn;
	reg	pll_lock_sync;
	(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
	reg	[35:0]	rxreg;
	wire  [2:0]   wire_sft100a_in;
	wire  [2:0]   wire_sft100a_out;
	wire  [2:0]   wire_sft101a_in;
	wire  [2:0]   wire_sft101a_out;
	wire  [2:0]   wire_sft102a_in;
	wire  [2:0]   wire_sft102a_out;
	wire  [2:0]   wire_sft103a_in;
	wire  [2:0]   wire_sft103a_out;
	wire  [1:0]   wire_sft116a_in;
	wire  [1:0]   wire_sft116a_out;
	wire  [1:0]   wire_sft117a_in;
	wire  [1:0]   wire_sft117a_out;
	wire  [1:0]   wire_sft118a_in;
	wire  [1:0]   wire_sft118a_out;
	wire  [1:0]   wire_sft119a_in;
	wire  [1:0]   wire_sft119a_out;
	wire  [1:0]   wire_sft11a_in;
	wire  [1:0]   wire_sft11a_out;
	wire  [2:0]   wire_sft121a_in;
	wire  [2:0]   wire_sft121a_out;
	wire  [2:0]   wire_sft122a_in;
	wire  [2:0]   wire_sft122a_out;
	wire  [2:0]   wire_sft123a_in;
	wire  [2:0]   wire_sft123a_out;
	wire  [2:0]   wire_sft124a_in;
	wire  [2:0]   wire_sft124a_out;
	wire  [1:0]   wire_sft12a_in;
	wire  [1:0]   wire_sft12a_out;
	wire  [1:0]   wire_sft137a_in;
	wire  [1:0]   wire_sft137a_out;
	wire  [1:0]   wire_sft138a_in;
	wire  [1:0]   wire_sft138a_out;
	wire  [1:0]   wire_sft139a_in;
	wire  [1:0]   wire_sft139a_out;
	wire  [1:0]   wire_sft13a_in;
	wire  [1:0]   wire_sft13a_out;
	wire  [1:0]   wire_sft140a_in;
	wire  [1:0]   wire_sft140a_out;
	wire  [2:0]   wire_sft142a_in;
	wire  [2:0]   wire_sft142a_out;
	wire  [2:0]   wire_sft143a_in;
	wire  [2:0]   wire_sft143a_out;
	wire  [2:0]   wire_sft144a_in;
	wire  [2:0]   wire_sft144a_out;
	wire  [2:0]   wire_sft145a_in;
	wire  [2:0]   wire_sft145a_out;
	wire  [1:0]   wire_sft14a_in;
	wire  [1:0]   wire_sft14a_out;
	wire  [1:0]   wire_sft158a_in;
	wire  [1:0]   wire_sft158a_out;
	wire  [1:0]   wire_sft159a_in;
	wire  [1:0]   wire_sft159a_out;
	wire  [1:0]   wire_sft160a_in;
	wire  [1:0]   wire_sft160a_out;
	wire  [1:0]   wire_sft161a_in;
	wire  [1:0]   wire_sft161a_out;
	wire  [2:0]   wire_sft163a_in;
	wire  [2:0]   wire_sft163a_out;
	wire  [2:0]   wire_sft164a_in;
	wire  [2:0]   wire_sft164a_out;
	wire  [2:0]   wire_sft165a_in;
	wire  [2:0]   wire_sft165a_out;
	wire  [2:0]   wire_sft166a_in;
	wire  [2:0]   wire_sft166a_out;
	wire  [2:0]   wire_sft16a_in;
	wire  [2:0]   wire_sft16a_out;
	wire  [1:0]   wire_sft179a_in;
	wire  [1:0]   wire_sft179a_out;
	wire  [2:0]   wire_sft17a_in;
	wire  [2:0]   wire_sft17a_out;
	wire  [1:0]   wire_sft180a_in;
	wire  [1:0]   wire_sft180a_out;
	wire  [1:0]   wire_sft181a_in;
	wire  [1:0]   wire_sft181a_out;
	wire  [1:0]   wire_sft182a_in;
	wire  [1:0]   wire_sft182a_out;
	wire  [2:0]   wire_sft184a_in;
	wire  [2:0]   wire_sft184a_out;
	wire  [2:0]   wire_sft185a_in;
	wire  [2:0]   wire_sft185a_out;
	wire  [2:0]   wire_sft186a_in;
	wire  [2:0]   wire_sft186a_out;
	wire  [2:0]   wire_sft187a_in;
	wire  [2:0]   wire_sft187a_out;
	wire  [2:0]   wire_sft18a_in;
	wire  [2:0]   wire_sft18a_out;
	wire  [2:0]   wire_sft19a_in;
	wire  [2:0]   wire_sft19a_out;
	wire  [1:0]   wire_sft32a_in;
	wire  [1:0]   wire_sft32a_out;
	wire  [1:0]   wire_sft33a_in;
	wire  [1:0]   wire_sft33a_out;
	wire  [1:0]   wire_sft34a_in;
	wire  [1:0]   wire_sft34a_out;
	wire  [1:0]   wire_sft35a_in;
	wire  [1:0]   wire_sft35a_out;
	wire  [2:0]   wire_sft37a_in;
	wire  [2:0]   wire_sft37a_out;
	wire  [2:0]   wire_sft38a_in;
	wire  [2:0]   wire_sft38a_out;
	wire  [2:0]   wire_sft39a_in;
	wire  [2:0]   wire_sft39a_out;
	wire  [2:0]   wire_sft40a_in;
	wire  [2:0]   wire_sft40a_out;
	wire  [1:0]   wire_sft53a_in;
	wire  [1:0]   wire_sft53a_out;
	wire  [1:0]   wire_sft54a_in;
	wire  [1:0]   wire_sft54a_out;
	wire  [1:0]   wire_sft55a_in;
	wire  [1:0]   wire_sft55a_out;
	wire  [1:0]   wire_sft56a_in;
	wire  [1:0]   wire_sft56a_out;
	wire  [2:0]   wire_sft58a_in;
	wire  [2:0]   wire_sft58a_out;
	wire  [2:0]   wire_sft59a_in;
	wire  [2:0]   wire_sft59a_out;
	wire  [2:0]   wire_sft60a_in;
	wire  [2:0]   wire_sft60a_out;
	wire  [2:0]   wire_sft61a_in;
	wire  [2:0]   wire_sft61a_out;
	wire  [1:0]   wire_sft74a_in;
	wire  [1:0]   wire_sft74a_out;
	wire  [1:0]   wire_sft75a_in;
	wire  [1:0]   wire_sft75a_out;
	wire  [1:0]   wire_sft76a_in;
	wire  [1:0]   wire_sft76a_out;
	wire  [1:0]   wire_sft77a_in;
	wire  [1:0]   wire_sft77a_out;
	wire  [2:0]   wire_sft79a_in;
	wire  [2:0]   wire_sft79a_out;
	wire  [2:0]   wire_sft80a_in;
	wire  [2:0]   wire_sft80a_out;
	wire  [2:0]   wire_sft81a_in;
	wire  [2:0]   wire_sft81a_out;
	wire  [2:0]   wire_sft82a_in;
	wire  [2:0]   wire_sft82a_out;
	wire  [1:0]   wire_sft95a_in;
	wire  [1:0]   wire_sft95a_out;
	wire  [1:0]   wire_sft96a_in;
	wire  [1:0]   wire_sft96a_out;
	wire  [1:0]   wire_sft97a_in;
	wire  [1:0]   wire_sft97a_out;
	wire  [1:0]   wire_sft98a_in;
	wire  [1:0]   wire_sft98a_out;
	wire  [8:0]   wire_rx_bitslip;
	wire  [8:0]   wire_rx_clk0;
	wire  [8:0]   wire_rx_datain;
	wire  [35:0]   wire_rx_dataout;
	wire  [8:0]   wire_rx_dpareset;
	wire  [8:0]   wire_rx_dpaswitch;
	wire  [8:0]   wire_rx_enable0;
	wire  [8:0]   wire_rx_fiforeset;
	wire  [6:0]   wire_pll_clk;
	wire  wire_pll_fbout;
	wire  wire_pll_locked;
	wire  [8:0]  dpa_lock_fifo_reset;
	wire  [8:0]  dpa_locked_out_wire;
	wire  [8:0]  dpa_locked_wire;
	wire  [8:0]  dpaswitch_wire;
	wire  [8:0]  int_dpa_locked_out_wire;
	wire  [8:0]  int_pll_kick_reset;
	wire  outclock;
	wire  pll_locked_out;
	wire  [35:0]  rx_out_wire;
	wire  [8:0]  w102w;
	wire  [0:0]  w112w;
	wire  [0:0]  w116w;
	wire  [0:0]  w120w;
	wire  [0:0]  w123w;
	wire  w129w;
	wire  [0:0]  w13w;
	wire  [2:0]  w144w;
	wire  [8:0]  w151w;
	wire  [0:0]  w161w;
	wire  [0:0]  w165w;
	wire  [0:0]  w169w;
	wire  [0:0]  w172w;
	wire  w178w;
	wire  [0:0]  w17w;
	wire  [2:0]  w193w;
	wire  [8:0]  w200w;
	wire  [0:0]  w210w;
	wire  [0:0]  w214w;
	wire  [0:0]  w218w;
	wire  [0:0]  w21w;
	wire  [0:0]  w221w;
	wire  w227w;
	wire  [8:0]  w249w;
	wire  [0:0]  w24w;
	wire  [0:0]  w259w;
	wire  [0:0]  w263w;
	wire  [0:0]  w267w;
	wire  [0:0]  w270w;
	wire  w276w;
	wire  [2:0]  w291w;
	wire  [8:0]  w298w;
	wire  [0:0]  w308w;
	wire  w30w;
	wire  [0:0]  w312w;
	wire  [0:0]  w316w;
	wire  [0:0]  w319w;
	wire  w325w;
	wire  [2:0]  w340w;
	wire  [8:0]  w347w;
	wire  [0:0]  w357w;
	wire  [0:0]  w361w;
	wire  [0:0]  w365w;
	wire  [0:0]  w368w;
	wire  w374w;
	wire  [2:0]  w389w;
	wire  [8:0]  w396w;
	wire  [8:0]  w3w;
	wire  [0:0]  w406w;
	wire  [0:0]  w410w;
	wire  [0:0]  w414w;
	wire  [0:0]  w417w;
	wire  w423w;
	wire  [2:0]  w438w;
	wire  [8:0]  w445w;
	wire  [2:0]  w45w;
	wire  [8:0]  w482w;
	wire  [8:0]  w494w;
	wire  [8:0]  w529w;
	wire  [8:0]  w539w;
	wire  [8:0]  w53w;
	wire  [8:0]  w574w;
	wire  [8:0]  w584w;
	wire  [8:0]  w619w;
	wire  [8:0]  w629w;
	wire  [0:0]  w63w;
	wire  [8:0]  w664w;
	wire  [8:0]  w674w;
	wire  [0:0]  w67w;
	wire  [8:0]  w709w;
	wire  [8:0]  w719w;
	wire  [0:0]  w71w;
	wire  [0:0]  w74w;
	wire  [8:0]  w754w;
	wire  [8:0]  w764w;
	wire  [8:0]  w799w;
	wire  [8:0]  w809w;
	wire  w80w;
	wire  [8:0]  w844w;
	wire  [2:0]  w95w;
	wire  w_sm_0448w;
	wire  w_sm_0497w;
	wire  w_sm_0542w;
	wire  w_sm_0587w;
	wire  w_sm_0632w;
	wire  w_sm_0677w;
	wire  w_sm_0722w;
	wire  w_sm_0767w;
	wire  w_sm_0812w;

	assign
		wire_add10_result = wire_sft11a_out + wire_sft12a_out + wire_sft13a_out;
	assign
		wire_add115_result = wire_sft116a_out + wire_sft117a_out + wire_sft118a_out;
	assign
		wire_add120_result = wire_sft121a_out + wire_sft122a_out + wire_sft123a_out;
	assign
		wire_add136_result = wire_sft137a_out + wire_sft138a_out + wire_sft139a_out;
	assign
		wire_add141_result = wire_sft142a_out + wire_sft143a_out + wire_sft144a_out;
	assign
		wire_add15_result = wire_sft16a_out + wire_sft17a_out + wire_sft18a_out;
	assign
		wire_add157_result = wire_sft158a_out + wire_sft159a_out + wire_sft160a_out;
	assign
		wire_add162_result = wire_sft163a_out + wire_sft164a_out + wire_sft165a_out;
	assign
		wire_add178_result = wire_sft179a_out + wire_sft180a_out + wire_sft181a_out;
	assign
		wire_add183_result = wire_sft184a_out + wire_sft185a_out + wire_sft186a_out;
	assign
		wire_add31_result = wire_sft32a_out + wire_sft33a_out + wire_sft34a_out;
	assign
		wire_add36_result = wire_sft37a_out + wire_sft38a_out + wire_sft39a_out;
	assign
		wire_add52_result = wire_sft53a_out + wire_sft54a_out + wire_sft55a_out;
	assign
		wire_add57_result = wire_sft58a_out + wire_sft59a_out + wire_sft60a_out;
	assign
		wire_add73_result = wire_sft74a_out + wire_sft75a_out + wire_sft76a_out;
	assign
		wire_add78_result = wire_sft79a_out + wire_sft80a_out + wire_sft81a_out;
	assign
		wire_add94_result = wire_sft95a_out + wire_sft96a_out + wire_sft97a_out;
	assign
		wire_add99_result = wire_sft100a_out + wire_sft101a_out + wire_sft102a_out;
	linki_v10_accum   lock_cnt_accum104a
	( 
	.aclr((w200w[4] | int_pll_kick_reset[4])),
	.clken((~ int_dpa_locked_out_wire[4])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum104a_cout),
	.data({dffe93, dffe91, dffe87}),
	.result(wire_lock_cnt_accum104a_result));
	linki_v10_accum   lock_cnt_accum125a
	( 
	.aclr((w249w[5] | int_pll_kick_reset[5])),
	.clken((~ int_dpa_locked_out_wire[5])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum125a_cout),
	.data(w291w));
	linki_v10_accum   lock_cnt_accum146a
	( 
	.aclr((w298w[6] | int_pll_kick_reset[6])),
	.clken((~ int_dpa_locked_out_wire[6])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum146a_cout),
	.data(w340w));
	linki_v10_accum   lock_cnt_accum167a
	( 
	.aclr((w347w[7] | int_pll_kick_reset[7])),
	.clken((~ int_dpa_locked_out_wire[7])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum167a_cout),
	.data(w389w));
	linki_v10_accum   lock_cnt_accum188a
	( 
	.aclr((w396w[8] | int_pll_kick_reset[8])),
	.clken((~ int_dpa_locked_out_wire[8])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum188a_cout),
	.data(w438w));
	linki_v10_accum   lock_cnt_accum20a
	( 
	.aclr((w3w[0] | int_pll_kick_reset[0])),
	.clken((~ int_dpa_locked_out_wire[0])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum20a_cout),
	.data(w45w));
	linki_v10_accum   lock_cnt_accum41a
	( 
	.aclr((w53w[1] | int_pll_kick_reset[1])),
	.clken((~ int_dpa_locked_out_wire[1])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum41a_cout),
	.data(w95w));
	linki_v10_accum   lock_cnt_accum62a
	( 
	.aclr((w102w[2] | int_pll_kick_reset[2])),
	.clken((~ int_dpa_locked_out_wire[2])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum62a_cout),
	.data(w144w));
	linki_v10_accum   lock_cnt_accum83a
	( 
	.aclr((w151w[3] | int_pll_kick_reset[3])),
	.clken((~ int_dpa_locked_out_wire[3])),
	.clock(outclock),
	.cout(wire_lock_cnt_accum83a_cout),
	.data(w193w));
	linki_v10_altclkctrl   rx_outclock_buf
	( 
	.inclk({{3{1'b0}}, wire_pll_clk[2]}),
	.outclk(wire_rx_outclock_buf_outclk));
	// synopsys translate_off
	initial
		dffe108 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe108_clrn)
		if (wire_dffe108_clrn == 1'b0) dffe108 <= 1'b0;
		else  dffe108 <= wire_sft124a_out[0];
	assign
		wire_dffe108_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		dffe109 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe109_clrn)
		if (wire_dffe109_clrn == 1'b0) dffe109 <= 1'b0;
		else  dffe109 <= w259w[0];
	assign
		wire_dffe109_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		dffe110 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe110_clrn)
		if (wire_dffe110_clrn == 1'b0) dffe110 <= 1'b0;
		else  dffe110 <= w263w[0];
	assign
		wire_dffe110_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		dffe111 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe111_clrn)
		if (wire_dffe111_clrn == 1'b0) dffe111 <= 1'b0;
		else  dffe111 <= wire_sft119a_out[0];
	assign
		wire_dffe111_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		dffe112 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe112_clrn)
		if (wire_dffe112_clrn == 1'b0) dffe112 <= 1'b0;
		else  dffe112 <= wire_sft124a_out[1];
	assign
		wire_dffe112_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		dffe113 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe113_clrn)
		if (wire_dffe113_clrn == 1'b0) dffe113 <= 1'b0;
		else  dffe113 <= wire_sft119a_out[1];
	assign
		wire_dffe113_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		dffe114 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe114_clrn)
		if (wire_dffe114_clrn == 1'b0) dffe114 <= 1'b0;
		else  dffe114 <= wire_sft124a_out[2];
	assign
		wire_dffe114_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		dffe129 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe129_clrn)
		if (wire_dffe129_clrn == 1'b0) dffe129 <= 1'b0;
		else  dffe129 <= wire_sft145a_out[0];
	assign
		wire_dffe129_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		dffe130 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe130_clrn)
		if (wire_dffe130_clrn == 1'b0) dffe130 <= 1'b0;
		else  dffe130 <= w308w[0];
	assign
		wire_dffe130_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		dffe131 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe131_clrn)
		if (wire_dffe131_clrn == 1'b0) dffe131 <= 1'b0;
		else  dffe131 <= w312w[0];
	assign
		wire_dffe131_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		dffe132 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe132_clrn)
		if (wire_dffe132_clrn == 1'b0) dffe132 <= 1'b0;
		else  dffe132 <= wire_sft140a_out[0];
	assign
		wire_dffe132_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		dffe133 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe133_clrn)
		if (wire_dffe133_clrn == 1'b0) dffe133 <= 1'b0;
		else  dffe133 <= wire_sft145a_out[1];
	assign
		wire_dffe133_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		dffe134 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe134_clrn)
		if (wire_dffe134_clrn == 1'b0) dffe134 <= 1'b0;
		else  dffe134 <= wire_sft140a_out[1];
	assign
		wire_dffe134_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		dffe135 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe135_clrn)
		if (wire_dffe135_clrn == 1'b0) dffe135 <= 1'b0;
		else  dffe135 <= wire_sft145a_out[2];
	assign
		wire_dffe135_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		dffe150 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe150_clrn)
		if (wire_dffe150_clrn == 1'b0) dffe150 <= 1'b0;
		else  dffe150 <= wire_sft166a_out[0];
	assign
		wire_dffe150_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		dffe151 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe151_clrn)
		if (wire_dffe151_clrn == 1'b0) dffe151 <= 1'b0;
		else  dffe151 <= w357w[0];
	assign
		wire_dffe151_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		dffe152 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe152_clrn)
		if (wire_dffe152_clrn == 1'b0) dffe152 <= 1'b0;
		else  dffe152 <= w361w[0];
	assign
		wire_dffe152_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		dffe153 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe153_clrn)
		if (wire_dffe153_clrn == 1'b0) dffe153 <= 1'b0;
		else  dffe153 <= wire_sft161a_out[0];
	assign
		wire_dffe153_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		dffe154 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe154_clrn)
		if (wire_dffe154_clrn == 1'b0) dffe154 <= 1'b0;
		else  dffe154 <= wire_sft166a_out[1];
	assign
		wire_dffe154_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		dffe155 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe155_clrn)
		if (wire_dffe155_clrn == 1'b0) dffe155 <= 1'b0;
		else  dffe155 <= wire_sft161a_out[1];
	assign
		wire_dffe155_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		dffe156 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe156_clrn)
		if (wire_dffe156_clrn == 1'b0) dffe156 <= 1'b0;
		else  dffe156 <= wire_sft166a_out[2];
	assign
		wire_dffe156_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		dffe171 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe171_clrn)
		if (wire_dffe171_clrn == 1'b0) dffe171 <= 1'b0;
		else  dffe171 <= wire_sft187a_out[0];
	assign
		wire_dffe171_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		dffe172 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe172_clrn)
		if (wire_dffe172_clrn == 1'b0) dffe172 <= 1'b0;
		else  dffe172 <= w406w[0];
	assign
		wire_dffe172_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		dffe173 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe173_clrn)
		if (wire_dffe173_clrn == 1'b0) dffe173 <= 1'b0;
		else  dffe173 <= w410w[0];
	assign
		wire_dffe173_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		dffe174 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe174_clrn)
		if (wire_dffe174_clrn == 1'b0) dffe174 <= 1'b0;
		else  dffe174 <= wire_sft182a_out[0];
	assign
		wire_dffe174_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		dffe175 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe175_clrn)
		if (wire_dffe175_clrn == 1'b0) dffe175 <= 1'b0;
		else  dffe175 <= wire_sft187a_out[1];
	assign
		wire_dffe175_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		dffe176 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe176_clrn)
		if (wire_dffe176_clrn == 1'b0) dffe176 <= 1'b0;
		else  dffe176 <= wire_sft182a_out[1];
	assign
		wire_dffe176_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		dffe177 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe177_clrn)
		if (wire_dffe177_clrn == 1'b0) dffe177 <= 1'b0;
		else  dffe177 <= wire_sft187a_out[2];
	assign
		wire_dffe177_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		dffe24 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe24_clrn)
		if (wire_dffe24_clrn == 1'b0) dffe24 <= 1'b0;
		else  dffe24 <= wire_sft40a_out[0];
	assign
		wire_dffe24_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		dffe25 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe25_clrn)
		if (wire_dffe25_clrn == 1'b0) dffe25 <= 1'b0;
		else  dffe25 <= w63w[0];
	assign
		wire_dffe25_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		dffe26 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe26_clrn)
		if (wire_dffe26_clrn == 1'b0) dffe26 <= 1'b0;
		else  dffe26 <= w67w[0];
	assign
		wire_dffe26_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		dffe27 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe27_clrn)
		if (wire_dffe27_clrn == 1'b0) dffe27 <= 1'b0;
		else  dffe27 <= wire_sft35a_out[0];
	assign
		wire_dffe27_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		dffe28 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe28_clrn)
		if (wire_dffe28_clrn == 1'b0) dffe28 <= 1'b0;
		else  dffe28 <= wire_sft40a_out[1];
	assign
		wire_dffe28_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		dffe29 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe29_clrn)
		if (wire_dffe29_clrn == 1'b0) dffe29 <= 1'b0;
		else  dffe29 <= wire_sft35a_out[1];
	assign
		wire_dffe29_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		dffe3 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe3_clrn)
		if (wire_dffe3_clrn == 1'b0) dffe3 <= 1'b0;
		else  dffe3 <= wire_sft19a_out[0];
	assign
		wire_dffe3_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		dffe30 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe30_clrn)
		if (wire_dffe30_clrn == 1'b0) dffe30 <= 1'b0;
		else  dffe30 <= wire_sft40a_out[2];
	assign
		wire_dffe30_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		dffe4 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe4_clrn)
		if (wire_dffe4_clrn == 1'b0) dffe4 <= 1'b0;
		else  dffe4 <= w13w[0];
	assign
		wire_dffe4_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		dffe45 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe45_clrn)
		if (wire_dffe45_clrn == 1'b0) dffe45 <= 1'b0;
		else  dffe45 <= wire_sft61a_out[0];
	assign
		wire_dffe45_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		dffe46 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe46_clrn)
		if (wire_dffe46_clrn == 1'b0) dffe46 <= 1'b0;
		else  dffe46 <= w112w[0];
	assign
		wire_dffe46_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		dffe47 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe47_clrn)
		if (wire_dffe47_clrn == 1'b0) dffe47 <= 1'b0;
		else  dffe47 <= w116w[0];
	assign
		wire_dffe47_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		dffe48 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe48_clrn)
		if (wire_dffe48_clrn == 1'b0) dffe48 <= 1'b0;
		else  dffe48 <= wire_sft56a_out[0];
	assign
		wire_dffe48_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		dffe49 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe49_clrn)
		if (wire_dffe49_clrn == 1'b0) dffe49 <= 1'b0;
		else  dffe49 <= wire_sft61a_out[1];
	assign
		wire_dffe49_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		dffe5 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe5_clrn)
		if (wire_dffe5_clrn == 1'b0) dffe5 <= 1'b0;
		else  dffe5 <= w17w[0];
	assign
		wire_dffe5_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		dffe50 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe50_clrn)
		if (wire_dffe50_clrn == 1'b0) dffe50 <= 1'b0;
		else  dffe50 <= wire_sft56a_out[1];
	assign
		wire_dffe50_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		dffe51 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe51_clrn)
		if (wire_dffe51_clrn == 1'b0) dffe51 <= 1'b0;
		else  dffe51 <= wire_sft61a_out[2];
	assign
		wire_dffe51_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		dffe6 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe6_clrn)
		if (wire_dffe6_clrn == 1'b0) dffe6 <= 1'b0;
		else  dffe6 <= wire_sft14a_out[0];
	assign
		wire_dffe6_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		dffe66 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe66_clrn)
		if (wire_dffe66_clrn == 1'b0) dffe66 <= 1'b0;
		else  dffe66 <= wire_sft82a_out[0];
	assign
		wire_dffe66_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		dffe67 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe67_clrn)
		if (wire_dffe67_clrn == 1'b0) dffe67 <= 1'b0;
		else  dffe67 <= w161w[0];
	assign
		wire_dffe67_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		dffe68 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe68_clrn)
		if (wire_dffe68_clrn == 1'b0) dffe68 <= 1'b0;
		else  dffe68 <= w165w[0];
	assign
		wire_dffe68_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		dffe69 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe69_clrn)
		if (wire_dffe69_clrn == 1'b0) dffe69 <= 1'b0;
		else  dffe69 <= wire_sft77a_out[0];
	assign
		wire_dffe69_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		dffe7 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe7_clrn)
		if (wire_dffe7_clrn == 1'b0) dffe7 <= 1'b0;
		else  dffe7 <= wire_sft19a_out[1];
	assign
		wire_dffe7_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		dffe70 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe70_clrn)
		if (wire_dffe70_clrn == 1'b0) dffe70 <= 1'b0;
		else  dffe70 <= wire_sft82a_out[1];
	assign
		wire_dffe70_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		dffe71 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe71_clrn)
		if (wire_dffe71_clrn == 1'b0) dffe71 <= 1'b0;
		else  dffe71 <= wire_sft77a_out[1];
	assign
		wire_dffe71_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		dffe72 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe72_clrn)
		if (wire_dffe72_clrn == 1'b0) dffe72 <= 1'b0;
		else  dffe72 <= wire_sft82a_out[2];
	assign
		wire_dffe72_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		dffe8 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe8_clrn)
		if (wire_dffe8_clrn == 1'b0) dffe8 <= 1'b0;
		else  dffe8 <= wire_sft14a_out[1];
	assign
		wire_dffe8_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		dffe87 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe87_clrn)
		if (wire_dffe87_clrn == 1'b0) dffe87 <= 1'b0;
		else  dffe87 <= wire_sft103a_out[0];
	assign
		wire_dffe87_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		dffe88 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe88_clrn)
		if (wire_dffe88_clrn == 1'b0) dffe88 <= 1'b0;
		else  dffe88 <= w210w[0];
	assign
		wire_dffe88_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		dffe89 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe89_clrn)
		if (wire_dffe89_clrn == 1'b0) dffe89 <= 1'b0;
		else  dffe89 <= w214w[0];
	assign
		wire_dffe89_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		dffe9 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe9_clrn)
		if (wire_dffe9_clrn == 1'b0) dffe9 <= 1'b0;
		else  dffe9 <= wire_sft19a_out[2];
	assign
		wire_dffe9_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		dffe90 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe90_clrn)
		if (wire_dffe90_clrn == 1'b0) dffe90 <= 1'b0;
		else  dffe90 <= wire_sft98a_out[0];
	assign
		wire_dffe90_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		dffe91 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe91_clrn)
		if (wire_dffe91_clrn == 1'b0) dffe91 <= 1'b0;
		else  dffe91 <= wire_sft103a_out[1];
	assign
		wire_dffe91_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		dffe92 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe92_clrn)
		if (wire_dffe92_clrn == 1'b0) dffe92 <= 1'b0;
		else  dffe92 <= wire_sft98a_out[1];
	assign
		wire_dffe92_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		dffe93 = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_dffe93_clrn)
		if (wire_dffe93_clrn == 1'b0) dffe93 <= 1'b0;
		else  dffe93 <= wire_sft103a_out[2];
	assign
		wire_dffe93_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		extra_reg107a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg107a_clrn)
		if (wire_extra_reg107a_clrn == 1'b0) extra_reg107a <= 1'b0;
		else  extra_reg107a <= pad_regr106a[0];
	assign
		wire_extra_reg107a_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		extra_reg128a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg128a_clrn)
		if (wire_extra_reg128a_clrn == 1'b0) extra_reg128a <= 1'b0;
		else  extra_reg128a <= pad_regr127a[0];
	assign
		wire_extra_reg128a_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		extra_reg149a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg149a_clrn)
		if (wire_extra_reg149a_clrn == 1'b0) extra_reg149a <= 1'b0;
		else  extra_reg149a <= pad_regr148a[0];
	assign
		wire_extra_reg149a_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		extra_reg170a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg170a_clrn)
		if (wire_extra_reg170a_clrn == 1'b0) extra_reg170a <= 1'b0;
		else  extra_reg170a <= pad_regr169a[0];
	assign
		wire_extra_reg170a_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		extra_reg23a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg23a_clrn)
		if (wire_extra_reg23a_clrn == 1'b0) extra_reg23a <= 1'b0;
		else  extra_reg23a <= pad_regr22a[0];
	assign
		wire_extra_reg23a_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		extra_reg2a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg2a_clrn)
		if (wire_extra_reg2a_clrn == 1'b0) extra_reg2a <= 1'b0;
		else  extra_reg2a <= pad_regr1a[0];
	assign
		wire_extra_reg2a_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		extra_reg44a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg44a_clrn)
		if (wire_extra_reg44a_clrn == 1'b0) extra_reg44a <= 1'b0;
		else  extra_reg44a <= pad_regr43a[0];
	assign
		wire_extra_reg44a_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		extra_reg65a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg65a_clrn)
		if (wire_extra_reg65a_clrn == 1'b0) extra_reg65a <= 1'b0;
		else  extra_reg65a <= pad_regr64a[0];
	assign
		wire_extra_reg65a_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		extra_reg86a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_extra_reg86a_clrn)
		if (wire_extra_reg86a_clrn == 1'b0) extra_reg86a <= 1'b0;
		else  extra_reg86a <= pad_regr85a[0];
	assign
		wire_extra_reg86a_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		lock_out_reg105a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg105a_clrn)
		if (wire_lock_out_reg105a_clrn == 1'b0) lock_out_reg105a <= 1'b0;
		else if  (wire_lock_cnt_accum104a_cout == 1'b1)   lock_out_reg105a <= 1'b1;
	assign
		wire_lock_out_reg105a_clrn = (~ (w200w[4] | int_pll_kick_reset[4]));
	// synopsys translate_off
	initial
		lock_out_reg126a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg126a_clrn)
		if (wire_lock_out_reg126a_clrn == 1'b0) lock_out_reg126a <= 1'b0;
		else if  (wire_lock_cnt_accum125a_cout == 1'b1)   lock_out_reg126a <= 1'b1;
	assign
		wire_lock_out_reg126a_clrn = (~ (w249w[5] | int_pll_kick_reset[5]));
	// synopsys translate_off
	initial
		lock_out_reg147a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg147a_clrn)
		if (wire_lock_out_reg147a_clrn == 1'b0) lock_out_reg147a <= 1'b0;
		else if  (wire_lock_cnt_accum146a_cout == 1'b1)   lock_out_reg147a <= 1'b1;
	assign
		wire_lock_out_reg147a_clrn = (~ (w298w[6] | int_pll_kick_reset[6]));
	// synopsys translate_off
	initial
		lock_out_reg168a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg168a_clrn)
		if (wire_lock_out_reg168a_clrn == 1'b0) lock_out_reg168a <= 1'b0;
		else if  (wire_lock_cnt_accum167a_cout == 1'b1)   lock_out_reg168a <= 1'b1;
	assign
		wire_lock_out_reg168a_clrn = (~ (w347w[7] | int_pll_kick_reset[7]));
	// synopsys translate_off
	initial
		lock_out_reg189a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg189a_clrn)
		if (wire_lock_out_reg189a_clrn == 1'b0) lock_out_reg189a <= 1'b0;
		else if  (wire_lock_cnt_accum188a_cout == 1'b1)   lock_out_reg189a <= 1'b1;
	assign
		wire_lock_out_reg189a_clrn = (~ (w396w[8] | int_pll_kick_reset[8]));
	// synopsys translate_off
	initial
		lock_out_reg21a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg21a_clrn)
		if (wire_lock_out_reg21a_clrn == 1'b0) lock_out_reg21a <= 1'b0;
		else if  (wire_lock_cnt_accum20a_cout == 1'b1)   lock_out_reg21a <= 1'b1;
	assign
		wire_lock_out_reg21a_clrn = (~ (w3w[0] | int_pll_kick_reset[0]));
	// synopsys translate_off
	initial
		lock_out_reg42a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg42a_clrn)
		if (wire_lock_out_reg42a_clrn == 1'b0) lock_out_reg42a <= 1'b0;
		else if  (wire_lock_cnt_accum41a_cout == 1'b1)   lock_out_reg42a <= 1'b1;
	assign
		wire_lock_out_reg42a_clrn = (~ (w53w[1] | int_pll_kick_reset[1]));
	// synopsys translate_off
	initial
		lock_out_reg63a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg63a_clrn)
		if (wire_lock_out_reg63a_clrn == 1'b0) lock_out_reg63a <= 1'b0;
		else if  (wire_lock_cnt_accum62a_cout == 1'b1)   lock_out_reg63a <= 1'b1;
	assign
		wire_lock_out_reg63a_clrn = (~ (w102w[2] | int_pll_kick_reset[2]));
	// synopsys translate_off
	initial
		lock_out_reg84a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg84a_clrn)
		if (wire_lock_out_reg84a_clrn == 1'b0) lock_out_reg84a <= 1'b0;
		else if  (wire_lock_cnt_accum83a_cout == 1'b1)   lock_out_reg84a <= 1'b1;
	assign
		wire_lock_out_reg84a_clrn = (~ (w151w[3] | int_pll_kick_reset[3]));
	// synopsys translate_off
	initial
		lock_out_reg_dly191a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly191a_clrn)
		if (wire_lock_out_reg_dly191a_clrn == 1'b0) lock_out_reg_dly191a <= 1'b0;
		else  lock_out_reg_dly191a <= int_dpa_locked_out_wire[0];
	assign
		wire_lock_out_reg_dly191a_clrn = (~ w482w[0]);
	// synopsys translate_off
	initial
		lock_out_reg_dly193a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly193a_clrn)
		if (wire_lock_out_reg_dly193a_clrn == 1'b0) lock_out_reg_dly193a <= 1'b0;
		else  lock_out_reg_dly193a <= int_dpa_locked_out_wire[1];
	assign
		wire_lock_out_reg_dly193a_clrn = (~ w529w[1]);
	// synopsys translate_off
	initial
		lock_out_reg_dly195a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly195a_clrn)
		if (wire_lock_out_reg_dly195a_clrn == 1'b0) lock_out_reg_dly195a <= 1'b0;
		else  lock_out_reg_dly195a <= int_dpa_locked_out_wire[2];
	assign
		wire_lock_out_reg_dly195a_clrn = (~ w574w[2]);
	// synopsys translate_off
	initial
		lock_out_reg_dly197a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly197a_clrn)
		if (wire_lock_out_reg_dly197a_clrn == 1'b0) lock_out_reg_dly197a <= 1'b0;
		else  lock_out_reg_dly197a <= int_dpa_locked_out_wire[3];
	assign
		wire_lock_out_reg_dly197a_clrn = (~ w619w[3]);
	// synopsys translate_off
	initial
		lock_out_reg_dly199a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly199a_clrn)
		if (wire_lock_out_reg_dly199a_clrn == 1'b0) lock_out_reg_dly199a <= 1'b0;
		else  lock_out_reg_dly199a <= int_dpa_locked_out_wire[4];
	assign
		wire_lock_out_reg_dly199a_clrn = (~ w664w[4]);
	// synopsys translate_off
	initial
		lock_out_reg_dly201a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly201a_clrn)
		if (wire_lock_out_reg_dly201a_clrn == 1'b0) lock_out_reg_dly201a <= 1'b0;
		else  lock_out_reg_dly201a <= int_dpa_locked_out_wire[5];
	assign
		wire_lock_out_reg_dly201a_clrn = (~ w709w[5]);
	// synopsys translate_off
	initial
		lock_out_reg_dly203a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly203a_clrn)
		if (wire_lock_out_reg_dly203a_clrn == 1'b0) lock_out_reg_dly203a <= 1'b0;
		else  lock_out_reg_dly203a <= int_dpa_locked_out_wire[6];
	assign
		wire_lock_out_reg_dly203a_clrn = (~ w754w[6]);
	// synopsys translate_off
	initial
		lock_out_reg_dly205a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly205a_clrn)
		if (wire_lock_out_reg_dly205a_clrn == 1'b0) lock_out_reg_dly205a <= 1'b0;
		else  lock_out_reg_dly205a <= int_dpa_locked_out_wire[7];
	assign
		wire_lock_out_reg_dly205a_clrn = (~ w799w[7]);
	// synopsys translate_off
	initial
		lock_out_reg_dly207a = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_out_reg_dly207a_clrn)
		if (wire_lock_out_reg_dly207a_clrn == 1'b0) lock_out_reg_dly207a <= 1'b0;
		else  lock_out_reg_dly207a <= int_dpa_locked_out_wire[8];
	assign
		wire_lock_out_reg_dly207a_clrn = (~ w844w[8]);
	// synopsys translate_off
	initial
		lock_state_mc190a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc190a_clrn[0:0])
		if (wire_lock_state_mc190a_clrn[0:0] == 1'b0) lock_state_mc190a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc190a_ena[0:0] == 1'b1)   lock_state_mc190a[0:0] <= wire_lock_state_mc190a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc190a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc190a_clrn[1:1])
		if (wire_lock_state_mc190a_clrn[1:1] == 1'b0) lock_state_mc190a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc190a_ena[1:1] == 1'b1)   lock_state_mc190a[1:1] <= wire_lock_state_mc190a_d[1:1];
	assign
		wire_lock_state_mc190a_d = {((((lock_state_mc190a[0] & (~ lock_state_mc190a[1])) & lock_out_reg_dly191a) | (((~ lock_state_mc190a[0]) & lock_state_mc190a[1]) & int_dpa_locked_out_wire[0])) & (~ (w_sm_0448w | (((~ lock_state_mc190a[0]) & (~ lock_state_mc190a[1])) & int_dpa_locked_out_wire[0])))), (((((~ lock_state_mc190a[0]) & (~ lock_state_mc190a[1])) & int_dpa_locked_out_wire[0]) | (((~ lock_state_mc190a[0]) & lock_state_mc190a[1]) & int_dpa_locked_out_wire[0])) & (~ (w_sm_0448w | ((lock_state_mc190a[0] & (~ lock_state_mc190a[1])) & lock_out_reg_dly191a))))};
	assign
		wire_lock_state_mc190a_ena = {2{(((w_sm_0448w | (((~ lock_state_mc190a[0]) & (~ lock_state_mc190a[1])) & int_dpa_locked_out_wire[0])) | ((lock_state_mc190a[0] & (~ lock_state_mc190a[1])) & lock_out_reg_dly191a)) | (((~ lock_state_mc190a[0]) & lock_state_mc190a[1]) & int_dpa_locked_out_wire[0]))}},
		wire_lock_state_mc190a_clrn = {2{(~ w445w[0])}};
	// synopsys translate_off
	initial
		lock_state_mc192a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc192a_clrn[0:0])
		if (wire_lock_state_mc192a_clrn[0:0] == 1'b0) lock_state_mc192a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc192a_ena[0:0] == 1'b1)   lock_state_mc192a[0:0] <= wire_lock_state_mc192a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc192a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc192a_clrn[1:1])
		if (wire_lock_state_mc192a_clrn[1:1] == 1'b0) lock_state_mc192a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc192a_ena[1:1] == 1'b1)   lock_state_mc192a[1:1] <= wire_lock_state_mc192a_d[1:1];
	assign
		wire_lock_state_mc192a_d = {((((lock_state_mc192a[0] & (~ lock_state_mc192a[1])) & lock_out_reg_dly193a) | (((~ lock_state_mc192a[0]) & lock_state_mc192a[1]) & int_dpa_locked_out_wire[1])) & (~ (w_sm_0497w | (((~ lock_state_mc192a[0]) & (~ lock_state_mc192a[1])) & int_dpa_locked_out_wire[1])))), (((((~ lock_state_mc192a[0]) & (~ lock_state_mc192a[1])) & int_dpa_locked_out_wire[1]) | (((~ lock_state_mc192a[0]) & lock_state_mc192a[1]) & int_dpa_locked_out_wire[1])) & (~ (w_sm_0497w | ((lock_state_mc192a[0] & (~ lock_state_mc192a[1])) & lock_out_reg_dly193a))))};
	assign
		wire_lock_state_mc192a_ena = {2{(((w_sm_0497w | (((~ lock_state_mc192a[0]) & (~ lock_state_mc192a[1])) & int_dpa_locked_out_wire[1])) | ((lock_state_mc192a[0] & (~ lock_state_mc192a[1])) & lock_out_reg_dly193a)) | (((~ lock_state_mc192a[0]) & lock_state_mc192a[1]) & int_dpa_locked_out_wire[1]))}},
		wire_lock_state_mc192a_clrn = {2{(~ w494w[1])}};
	// synopsys translate_off
	initial
		lock_state_mc194a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc194a_clrn[0:0])
		if (wire_lock_state_mc194a_clrn[0:0] == 1'b0) lock_state_mc194a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc194a_ena[0:0] == 1'b1)   lock_state_mc194a[0:0] <= wire_lock_state_mc194a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc194a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc194a_clrn[1:1])
		if (wire_lock_state_mc194a_clrn[1:1] == 1'b0) lock_state_mc194a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc194a_ena[1:1] == 1'b1)   lock_state_mc194a[1:1] <= wire_lock_state_mc194a_d[1:1];
	assign
		wire_lock_state_mc194a_d = {((((lock_state_mc194a[0] & (~ lock_state_mc194a[1])) & lock_out_reg_dly195a) | (((~ lock_state_mc194a[0]) & lock_state_mc194a[1]) & int_dpa_locked_out_wire[2])) & (~ (w_sm_0542w | (((~ lock_state_mc194a[0]) & (~ lock_state_mc194a[1])) & int_dpa_locked_out_wire[2])))), (((((~ lock_state_mc194a[0]) & (~ lock_state_mc194a[1])) & int_dpa_locked_out_wire[2]) | (((~ lock_state_mc194a[0]) & lock_state_mc194a[1]) & int_dpa_locked_out_wire[2])) & (~ (w_sm_0542w | ((lock_state_mc194a[0] & (~ lock_state_mc194a[1])) & lock_out_reg_dly195a))))};
	assign
		wire_lock_state_mc194a_ena = {2{(((w_sm_0542w | (((~ lock_state_mc194a[0]) & (~ lock_state_mc194a[1])) & int_dpa_locked_out_wire[2])) | ((lock_state_mc194a[0] & (~ lock_state_mc194a[1])) & lock_out_reg_dly195a)) | (((~ lock_state_mc194a[0]) & lock_state_mc194a[1]) & int_dpa_locked_out_wire[2]))}},
		wire_lock_state_mc194a_clrn = {2{(~ w539w[2])}};
	// synopsys translate_off
	initial
		lock_state_mc196a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc196a_clrn[0:0])
		if (wire_lock_state_mc196a_clrn[0:0] == 1'b0) lock_state_mc196a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc196a_ena[0:0] == 1'b1)   lock_state_mc196a[0:0] <= wire_lock_state_mc196a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc196a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc196a_clrn[1:1])
		if (wire_lock_state_mc196a_clrn[1:1] == 1'b0) lock_state_mc196a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc196a_ena[1:1] == 1'b1)   lock_state_mc196a[1:1] <= wire_lock_state_mc196a_d[1:1];
	assign
		wire_lock_state_mc196a_d = {((((lock_state_mc196a[0] & (~ lock_state_mc196a[1])) & lock_out_reg_dly197a) | (((~ lock_state_mc196a[0]) & lock_state_mc196a[1]) & int_dpa_locked_out_wire[3])) & (~ (w_sm_0587w | (((~ lock_state_mc196a[0]) & (~ lock_state_mc196a[1])) & int_dpa_locked_out_wire[3])))), (((((~ lock_state_mc196a[0]) & (~ lock_state_mc196a[1])) & int_dpa_locked_out_wire[3]) | (((~ lock_state_mc196a[0]) & lock_state_mc196a[1]) & int_dpa_locked_out_wire[3])) & (~ (w_sm_0587w | ((lock_state_mc196a[0] & (~ lock_state_mc196a[1])) & lock_out_reg_dly197a))))};
	assign
		wire_lock_state_mc196a_ena = {2{(((w_sm_0587w | (((~ lock_state_mc196a[0]) & (~ lock_state_mc196a[1])) & int_dpa_locked_out_wire[3])) | ((lock_state_mc196a[0] & (~ lock_state_mc196a[1])) & lock_out_reg_dly197a)) | (((~ lock_state_mc196a[0]) & lock_state_mc196a[1]) & int_dpa_locked_out_wire[3]))}},
		wire_lock_state_mc196a_clrn = {2{(~ w584w[3])}};
	// synopsys translate_off
	initial
		lock_state_mc198a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc198a_clrn[0:0])
		if (wire_lock_state_mc198a_clrn[0:0] == 1'b0) lock_state_mc198a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc198a_ena[0:0] == 1'b1)   lock_state_mc198a[0:0] <= wire_lock_state_mc198a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc198a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc198a_clrn[1:1])
		if (wire_lock_state_mc198a_clrn[1:1] == 1'b0) lock_state_mc198a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc198a_ena[1:1] == 1'b1)   lock_state_mc198a[1:1] <= wire_lock_state_mc198a_d[1:1];
	assign
		wire_lock_state_mc198a_d = {((((lock_state_mc198a[0] & (~ lock_state_mc198a[1])) & lock_out_reg_dly199a) | (((~ lock_state_mc198a[0]) & lock_state_mc198a[1]) & int_dpa_locked_out_wire[4])) & (~ (w_sm_0632w | (((~ lock_state_mc198a[0]) & (~ lock_state_mc198a[1])) & int_dpa_locked_out_wire[4])))), (((((~ lock_state_mc198a[0]) & (~ lock_state_mc198a[1])) & int_dpa_locked_out_wire[4]) | (((~ lock_state_mc198a[0]) & lock_state_mc198a[1]) & int_dpa_locked_out_wire[4])) & (~ (w_sm_0632w | ((lock_state_mc198a[0] & (~ lock_state_mc198a[1])) & lock_out_reg_dly199a))))};
	assign
		wire_lock_state_mc198a_ena = {2{(((w_sm_0632w | (((~ lock_state_mc198a[0]) & (~ lock_state_mc198a[1])) & int_dpa_locked_out_wire[4])) | ((lock_state_mc198a[0] & (~ lock_state_mc198a[1])) & lock_out_reg_dly199a)) | (((~ lock_state_mc198a[0]) & lock_state_mc198a[1]) & int_dpa_locked_out_wire[4]))}},
		wire_lock_state_mc198a_clrn = {2{(~ w629w[4])}};
	// synopsys translate_off
	initial
		lock_state_mc200a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc200a_clrn[0:0])
		if (wire_lock_state_mc200a_clrn[0:0] == 1'b0) lock_state_mc200a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc200a_ena[0:0] == 1'b1)   lock_state_mc200a[0:0] <= wire_lock_state_mc200a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc200a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc200a_clrn[1:1])
		if (wire_lock_state_mc200a_clrn[1:1] == 1'b0) lock_state_mc200a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc200a_ena[1:1] == 1'b1)   lock_state_mc200a[1:1] <= wire_lock_state_mc200a_d[1:1];
	assign
		wire_lock_state_mc200a_d = {((((lock_state_mc200a[0] & (~ lock_state_mc200a[1])) & lock_out_reg_dly201a) | (((~ lock_state_mc200a[0]) & lock_state_mc200a[1]) & int_dpa_locked_out_wire[5])) & (~ (w_sm_0677w | (((~ lock_state_mc200a[0]) & (~ lock_state_mc200a[1])) & int_dpa_locked_out_wire[5])))), (((((~ lock_state_mc200a[0]) & (~ lock_state_mc200a[1])) & int_dpa_locked_out_wire[5]) | (((~ lock_state_mc200a[0]) & lock_state_mc200a[1]) & int_dpa_locked_out_wire[5])) & (~ (w_sm_0677w | ((lock_state_mc200a[0] & (~ lock_state_mc200a[1])) & lock_out_reg_dly201a))))};
	assign
		wire_lock_state_mc200a_ena = {2{(((w_sm_0677w | (((~ lock_state_mc200a[0]) & (~ lock_state_mc200a[1])) & int_dpa_locked_out_wire[5])) | ((lock_state_mc200a[0] & (~ lock_state_mc200a[1])) & lock_out_reg_dly201a)) | (((~ lock_state_mc200a[0]) & lock_state_mc200a[1]) & int_dpa_locked_out_wire[5]))}},
		wire_lock_state_mc200a_clrn = {2{(~ w674w[5])}};
	// synopsys translate_off
	initial
		lock_state_mc202a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc202a_clrn[0:0])
		if (wire_lock_state_mc202a_clrn[0:0] == 1'b0) lock_state_mc202a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc202a_ena[0:0] == 1'b1)   lock_state_mc202a[0:0] <= wire_lock_state_mc202a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc202a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc202a_clrn[1:1])
		if (wire_lock_state_mc202a_clrn[1:1] == 1'b0) lock_state_mc202a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc202a_ena[1:1] == 1'b1)   lock_state_mc202a[1:1] <= wire_lock_state_mc202a_d[1:1];
	assign
		wire_lock_state_mc202a_d = {((((lock_state_mc202a[0] & (~ lock_state_mc202a[1])) & lock_out_reg_dly203a) | (((~ lock_state_mc202a[0]) & lock_state_mc202a[1]) & int_dpa_locked_out_wire[6])) & (~ (w_sm_0722w | (((~ lock_state_mc202a[0]) & (~ lock_state_mc202a[1])) & int_dpa_locked_out_wire[6])))), (((((~ lock_state_mc202a[0]) & (~ lock_state_mc202a[1])) & int_dpa_locked_out_wire[6]) | (((~ lock_state_mc202a[0]) & lock_state_mc202a[1]) & int_dpa_locked_out_wire[6])) & (~ (w_sm_0722w | ((lock_state_mc202a[0] & (~ lock_state_mc202a[1])) & lock_out_reg_dly203a))))};
	assign
		wire_lock_state_mc202a_ena = {2{(((w_sm_0722w | (((~ lock_state_mc202a[0]) & (~ lock_state_mc202a[1])) & int_dpa_locked_out_wire[6])) | ((lock_state_mc202a[0] & (~ lock_state_mc202a[1])) & lock_out_reg_dly203a)) | (((~ lock_state_mc202a[0]) & lock_state_mc202a[1]) & int_dpa_locked_out_wire[6]))}},
		wire_lock_state_mc202a_clrn = {2{(~ w719w[6])}};
	// synopsys translate_off
	initial
		lock_state_mc204a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc204a_clrn[0:0])
		if (wire_lock_state_mc204a_clrn[0:0] == 1'b0) lock_state_mc204a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc204a_ena[0:0] == 1'b1)   lock_state_mc204a[0:0] <= wire_lock_state_mc204a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc204a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc204a_clrn[1:1])
		if (wire_lock_state_mc204a_clrn[1:1] == 1'b0) lock_state_mc204a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc204a_ena[1:1] == 1'b1)   lock_state_mc204a[1:1] <= wire_lock_state_mc204a_d[1:1];
	assign
		wire_lock_state_mc204a_d = {((((lock_state_mc204a[0] & (~ lock_state_mc204a[1])) & lock_out_reg_dly205a) | (((~ lock_state_mc204a[0]) & lock_state_mc204a[1]) & int_dpa_locked_out_wire[7])) & (~ (w_sm_0767w | (((~ lock_state_mc204a[0]) & (~ lock_state_mc204a[1])) & int_dpa_locked_out_wire[7])))), (((((~ lock_state_mc204a[0]) & (~ lock_state_mc204a[1])) & int_dpa_locked_out_wire[7]) | (((~ lock_state_mc204a[0]) & lock_state_mc204a[1]) & int_dpa_locked_out_wire[7])) & (~ (w_sm_0767w | ((lock_state_mc204a[0] & (~ lock_state_mc204a[1])) & lock_out_reg_dly205a))))};
	assign
		wire_lock_state_mc204a_ena = {2{(((w_sm_0767w | (((~ lock_state_mc204a[0]) & (~ lock_state_mc204a[1])) & int_dpa_locked_out_wire[7])) | ((lock_state_mc204a[0] & (~ lock_state_mc204a[1])) & lock_out_reg_dly205a)) | (((~ lock_state_mc204a[0]) & lock_state_mc204a[1]) & int_dpa_locked_out_wire[7]))}},
		wire_lock_state_mc204a_clrn = {2{(~ w764w[7])}};
	// synopsys translate_off
	initial
		lock_state_mc206a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc206a_clrn[0:0])
		if (wire_lock_state_mc206a_clrn[0:0] == 1'b0) lock_state_mc206a[0:0] <= 1'b0;
		else if  (wire_lock_state_mc206a_ena[0:0] == 1'b1)   lock_state_mc206a[0:0] <= wire_lock_state_mc206a_d[0:0];
	// synopsys translate_off
	initial
		lock_state_mc206a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_lock_state_mc206a_clrn[1:1])
		if (wire_lock_state_mc206a_clrn[1:1] == 1'b0) lock_state_mc206a[1:1] <= 1'b0;
		else if  (wire_lock_state_mc206a_ena[1:1] == 1'b1)   lock_state_mc206a[1:1] <= wire_lock_state_mc206a_d[1:1];
	assign
		wire_lock_state_mc206a_d = {((((lock_state_mc206a[0] & (~ lock_state_mc206a[1])) & lock_out_reg_dly207a) | (((~ lock_state_mc206a[0]) & lock_state_mc206a[1]) & int_dpa_locked_out_wire[8])) & (~ (w_sm_0812w | (((~ lock_state_mc206a[0]) & (~ lock_state_mc206a[1])) & int_dpa_locked_out_wire[8])))), (((((~ lock_state_mc206a[0]) & (~ lock_state_mc206a[1])) & int_dpa_locked_out_wire[8]) | (((~ lock_state_mc206a[0]) & lock_state_mc206a[1]) & int_dpa_locked_out_wire[8])) & (~ (w_sm_0812w | ((lock_state_mc206a[0] & (~ lock_state_mc206a[1])) & lock_out_reg_dly207a))))};
	assign
		wire_lock_state_mc206a_ena = {2{(((w_sm_0812w | (((~ lock_state_mc206a[0]) & (~ lock_state_mc206a[1])) & int_dpa_locked_out_wire[8])) | ((lock_state_mc206a[0] & (~ lock_state_mc206a[1])) & lock_out_reg_dly207a)) | (((~ lock_state_mc206a[0]) & lock_state_mc206a[1]) & int_dpa_locked_out_wire[8]))}},
		wire_lock_state_mc206a_clrn = {2{(~ w809w[8])}};
	// synopsys translate_off
	initial
		pad_regr106a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr106a_clrn[0:0])
		if (wire_pad_regr106a_clrn[0:0] == 1'b0) pad_regr106a[0:0] <= 1'b0;
		else  pad_regr106a[0:0] <= wire_pad_regr106a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr106a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr106a_clrn[1:1])
		if (wire_pad_regr106a_clrn[1:1] == 1'b0) pad_regr106a[1:1] <= 1'b0;
		else  pad_regr106a[1:1] <= wire_pad_regr106a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr106a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr106a_clrn[2:2])
		if (wire_pad_regr106a_clrn[2:2] == 1'b0) pad_regr106a[2:2] <= 1'b0;
		else  pad_regr106a[2:2] <= wire_pad_regr106a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr106a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr106a_clrn[3:3])
		if (wire_pad_regr106a_clrn[3:3] == 1'b0) pad_regr106a[3:3] <= 1'b0;
		else  pad_regr106a[3:3] <= wire_pad_regr106a_d[3:3];
	assign
		wire_pad_regr106a_d = rx_out_wire[23:20];
	assign
		wire_pad_regr106a_clrn = {4{(~ (w249w[5] | int_pll_kick_reset[5]))}};
	// synopsys translate_off
	initial
		pad_regr127a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr127a_clrn[0:0])
		if (wire_pad_regr127a_clrn[0:0] == 1'b0) pad_regr127a[0:0] <= 1'b0;
		else  pad_regr127a[0:0] <= wire_pad_regr127a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr127a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr127a_clrn[1:1])
		if (wire_pad_regr127a_clrn[1:1] == 1'b0) pad_regr127a[1:1] <= 1'b0;
		else  pad_regr127a[1:1] <= wire_pad_regr127a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr127a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr127a_clrn[2:2])
		if (wire_pad_regr127a_clrn[2:2] == 1'b0) pad_regr127a[2:2] <= 1'b0;
		else  pad_regr127a[2:2] <= wire_pad_regr127a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr127a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr127a_clrn[3:3])
		if (wire_pad_regr127a_clrn[3:3] == 1'b0) pad_regr127a[3:3] <= 1'b0;
		else  pad_regr127a[3:3] <= wire_pad_regr127a_d[3:3];
	assign
		wire_pad_regr127a_d = rx_out_wire[27:24];
	assign
		wire_pad_regr127a_clrn = {4{(~ (w298w[6] | int_pll_kick_reset[6]))}};
	// synopsys translate_off
	initial
		pad_regr148a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr148a_clrn[0:0])
		if (wire_pad_regr148a_clrn[0:0] == 1'b0) pad_regr148a[0:0] <= 1'b0;
		else  pad_regr148a[0:0] <= wire_pad_regr148a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr148a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr148a_clrn[1:1])
		if (wire_pad_regr148a_clrn[1:1] == 1'b0) pad_regr148a[1:1] <= 1'b0;
		else  pad_regr148a[1:1] <= wire_pad_regr148a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr148a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr148a_clrn[2:2])
		if (wire_pad_regr148a_clrn[2:2] == 1'b0) pad_regr148a[2:2] <= 1'b0;
		else  pad_regr148a[2:2] <= wire_pad_regr148a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr148a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr148a_clrn[3:3])
		if (wire_pad_regr148a_clrn[3:3] == 1'b0) pad_regr148a[3:3] <= 1'b0;
		else  pad_regr148a[3:3] <= wire_pad_regr148a_d[3:3];
	assign
		wire_pad_regr148a_d = rx_out_wire[31:28];
	assign
		wire_pad_regr148a_clrn = {4{(~ (w347w[7] | int_pll_kick_reset[7]))}};
	// synopsys translate_off
	initial
		pad_regr169a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr169a_clrn[0:0])
		if (wire_pad_regr169a_clrn[0:0] == 1'b0) pad_regr169a[0:0] <= 1'b0;
		else  pad_regr169a[0:0] <= wire_pad_regr169a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr169a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr169a_clrn[1:1])
		if (wire_pad_regr169a_clrn[1:1] == 1'b0) pad_regr169a[1:1] <= 1'b0;
		else  pad_regr169a[1:1] <= wire_pad_regr169a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr169a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr169a_clrn[2:2])
		if (wire_pad_regr169a_clrn[2:2] == 1'b0) pad_regr169a[2:2] <= 1'b0;
		else  pad_regr169a[2:2] <= wire_pad_regr169a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr169a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr169a_clrn[3:3])
		if (wire_pad_regr169a_clrn[3:3] == 1'b0) pad_regr169a[3:3] <= 1'b0;
		else  pad_regr169a[3:3] <= wire_pad_regr169a_d[3:3];
	assign
		wire_pad_regr169a_d = rx_out_wire[35:32];
	assign
		wire_pad_regr169a_clrn = {4{(~ (w396w[8] | int_pll_kick_reset[8]))}};
	// synopsys translate_off
	initial
		pad_regr1a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr1a_clrn[0:0])
		if (wire_pad_regr1a_clrn[0:0] == 1'b0) pad_regr1a[0:0] <= 1'b0;
		else  pad_regr1a[0:0] <= wire_pad_regr1a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr1a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr1a_clrn[1:1])
		if (wire_pad_regr1a_clrn[1:1] == 1'b0) pad_regr1a[1:1] <= 1'b0;
		else  pad_regr1a[1:1] <= wire_pad_regr1a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr1a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr1a_clrn[2:2])
		if (wire_pad_regr1a_clrn[2:2] == 1'b0) pad_regr1a[2:2] <= 1'b0;
		else  pad_regr1a[2:2] <= wire_pad_regr1a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr1a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr1a_clrn[3:3])
		if (wire_pad_regr1a_clrn[3:3] == 1'b0) pad_regr1a[3:3] <= 1'b0;
		else  pad_regr1a[3:3] <= wire_pad_regr1a_d[3:3];
	assign
		wire_pad_regr1a_d = rx_out_wire[3:0];
	assign
		wire_pad_regr1a_clrn = {4{(~ (w3w[0] | int_pll_kick_reset[0]))}};
	// synopsys translate_off
	initial
		pad_regr22a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr22a_clrn[0:0])
		if (wire_pad_regr22a_clrn[0:0] == 1'b0) pad_regr22a[0:0] <= 1'b0;
		else  pad_regr22a[0:0] <= wire_pad_regr22a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr22a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr22a_clrn[1:1])
		if (wire_pad_regr22a_clrn[1:1] == 1'b0) pad_regr22a[1:1] <= 1'b0;
		else  pad_regr22a[1:1] <= wire_pad_regr22a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr22a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr22a_clrn[2:2])
		if (wire_pad_regr22a_clrn[2:2] == 1'b0) pad_regr22a[2:2] <= 1'b0;
		else  pad_regr22a[2:2] <= wire_pad_regr22a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr22a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr22a_clrn[3:3])
		if (wire_pad_regr22a_clrn[3:3] == 1'b0) pad_regr22a[3:3] <= 1'b0;
		else  pad_regr22a[3:3] <= wire_pad_regr22a_d[3:3];
	assign
		wire_pad_regr22a_d = rx_out_wire[7:4];
	assign
		wire_pad_regr22a_clrn = {4{(~ (w53w[1] | int_pll_kick_reset[1]))}};
	// synopsys translate_off
	initial
		pad_regr43a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr43a_clrn[0:0])
		if (wire_pad_regr43a_clrn[0:0] == 1'b0) pad_regr43a[0:0] <= 1'b0;
		else  pad_regr43a[0:0] <= wire_pad_regr43a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr43a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr43a_clrn[1:1])
		if (wire_pad_regr43a_clrn[1:1] == 1'b0) pad_regr43a[1:1] <= 1'b0;
		else  pad_regr43a[1:1] <= wire_pad_regr43a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr43a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr43a_clrn[2:2])
		if (wire_pad_regr43a_clrn[2:2] == 1'b0) pad_regr43a[2:2] <= 1'b0;
		else  pad_regr43a[2:2] <= wire_pad_regr43a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr43a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr43a_clrn[3:3])
		if (wire_pad_regr43a_clrn[3:3] == 1'b0) pad_regr43a[3:3] <= 1'b0;
		else  pad_regr43a[3:3] <= wire_pad_regr43a_d[3:3];
	assign
		wire_pad_regr43a_d = rx_out_wire[11:8];
	assign
		wire_pad_regr43a_clrn = {4{(~ (w102w[2] | int_pll_kick_reset[2]))}};
	// synopsys translate_off
	initial
		pad_regr64a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr64a_clrn[0:0])
		if (wire_pad_regr64a_clrn[0:0] == 1'b0) pad_regr64a[0:0] <= 1'b0;
		else  pad_regr64a[0:0] <= wire_pad_regr64a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr64a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr64a_clrn[1:1])
		if (wire_pad_regr64a_clrn[1:1] == 1'b0) pad_regr64a[1:1] <= 1'b0;
		else  pad_regr64a[1:1] <= wire_pad_regr64a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr64a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr64a_clrn[2:2])
		if (wire_pad_regr64a_clrn[2:2] == 1'b0) pad_regr64a[2:2] <= 1'b0;
		else  pad_regr64a[2:2] <= wire_pad_regr64a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr64a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr64a_clrn[3:3])
		if (wire_pad_regr64a_clrn[3:3] == 1'b0) pad_regr64a[3:3] <= 1'b0;
		else  pad_regr64a[3:3] <= wire_pad_regr64a_d[3:3];
	assign
		wire_pad_regr64a_d = rx_out_wire[15:12];
	assign
		wire_pad_regr64a_clrn = {4{(~ (w151w[3] | int_pll_kick_reset[3]))}};
	// synopsys translate_off
	initial
		pad_regr85a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr85a_clrn[0:0])
		if (wire_pad_regr85a_clrn[0:0] == 1'b0) pad_regr85a[0:0] <= 1'b0;
		else  pad_regr85a[0:0] <= wire_pad_regr85a_d[0:0];
	// synopsys translate_off
	initial
		pad_regr85a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr85a_clrn[1:1])
		if (wire_pad_regr85a_clrn[1:1] == 1'b0) pad_regr85a[1:1] <= 1'b0;
		else  pad_regr85a[1:1] <= wire_pad_regr85a_d[1:1];
	// synopsys translate_off
	initial
		pad_regr85a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr85a_clrn[2:2])
		if (wire_pad_regr85a_clrn[2:2] == 1'b0) pad_regr85a[2:2] <= 1'b0;
		else  pad_regr85a[2:2] <= wire_pad_regr85a_d[2:2];
	// synopsys translate_off
	initial
		pad_regr85a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge outclock or  negedge wire_pad_regr85a_clrn[3:3])
		if (wire_pad_regr85a_clrn[3:3] == 1'b0) pad_regr85a[3:3] <= 1'b0;
		else  pad_regr85a[3:3] <= wire_pad_regr85a_d[3:3];
	assign
		wire_pad_regr85a_d = rx_out_wire[19:16];
	assign
		wire_pad_regr85a_clrn = {4{(~ (w200w[4] | int_pll_kick_reset[4]))}};
	// synopsys translate_off
	initial
		pll_lock_sync = 0;
	// synopsys translate_on
	always @ ( posedge wire_pll_locked or  posedge pll_areset)
		if (pll_areset == 1'b1) pll_lock_sync <= 1'b0;
		else  pll_lock_sync <= 1'b1;
	// synopsys translate_off
	initial
		rxreg = 0;
	// synopsys translate_on
	always @ ( posedge outclock)
		  rxreg <= wire_rx_dataout;
	soft   sft100a_0
	( 
	.in(wire_sft100a_in[0:0]),
	.out(wire_sft100a_out[0:0]));
	soft   sft100a_1
	( 
	.in(wire_sft100a_in[1:1]),
	.out(wire_sft100a_out[1:1]));
	soft   sft100a_2
	( 
	.in(wire_sft100a_in[2:2]),
	.out(wire_sft100a_out[2:2]));
	assign
		wire_sft100a_in = {w227w, {dffe92, dffe88}};
	soft   sft101a_0
	( 
	.in(wire_sft101a_in[0:0]),
	.out(wire_sft101a_out[0:0]));
	soft   sft101a_1
	( 
	.in(wire_sft101a_in[1:1]),
	.out(wire_sft101a_out[1:1]));
	soft   sft101a_2
	( 
	.in(wire_sft101a_in[2:2]),
	.out(wire_sft101a_out[2:2]));
	assign
		wire_sft101a_in = {w227w, {w227w, dffe89}};
	soft   sft102a_0
	( 
	.in(wire_sft102a_in[0:0]),
	.out(wire_sft102a_out[0:0]));
	soft   sft102a_1
	( 
	.in(wire_sft102a_in[1:1]),
	.out(wire_sft102a_out[1:1]));
	soft   sft102a_2
	( 
	.in(wire_sft102a_in[2:2]),
	.out(wire_sft102a_out[2:2]));
	assign
		wire_sft102a_in = {w227w, {w227w, dffe90}};
	soft   sft103a_0
	( 
	.in(wire_sft103a_in[0:0]),
	.out(wire_sft103a_out[0:0]));
	soft   sft103a_1
	( 
	.in(wire_sft103a_in[1:1]),
	.out(wire_sft103a_out[1:1]));
	soft   sft103a_2
	( 
	.in(wire_sft103a_in[2:2]),
	.out(wire_sft103a_out[2:2]));
	assign
		wire_sft103a_in = wire_add99_result;
	soft   sft116a_0
	( 
	.in(wire_sft116a_in[0:0]),
	.out(wire_sft116a_out[0:0]));
	soft   sft116a_1
	( 
	.in(wire_sft116a_in[1:1]),
	.out(wire_sft116a_out[1:1]));
	assign
		wire_sft116a_in = {w276w, w270w[0]};
	soft   sft117a_0
	( 
	.in(wire_sft117a_in[0:0]),
	.out(wire_sft117a_out[0:0]));
	soft   sft117a_1
	( 
	.in(wire_sft117a_in[1:1]),
	.out(wire_sft117a_out[1:1]));
	assign
		wire_sft117a_in = {w276w, w267w[0]};
	soft   sft118a_0
	( 
	.in(wire_sft118a_in[0:0]),
	.out(wire_sft118a_out[0:0]));
	soft   sft118a_1
	( 
	.in(wire_sft118a_in[1:1]),
	.out(wire_sft118a_out[1:1]));
	assign
		wire_sft118a_in = {2{w276w}};
	soft   sft119a_0
	( 
	.in(wire_sft119a_in[0:0]),
	.out(wire_sft119a_out[0:0]));
	soft   sft119a_1
	( 
	.in(wire_sft119a_in[1:1]),
	.out(wire_sft119a_out[1:1]));
	assign
		wire_sft119a_in = wire_add115_result;
	soft   sft11a_0
	( 
	.in(wire_sft11a_in[0:0]),
	.out(wire_sft11a_out[0:0]));
	soft   sft11a_1
	( 
	.in(wire_sft11a_in[1:1]),
	.out(wire_sft11a_out[1:1]));
	assign
		wire_sft11a_in = {w30w, w24w[0]};
	soft   sft121a_0
	( 
	.in(wire_sft121a_in[0:0]),
	.out(wire_sft121a_out[0:0]));
	soft   sft121a_1
	( 
	.in(wire_sft121a_in[1:1]),
	.out(wire_sft121a_out[1:1]));
	soft   sft121a_2
	( 
	.in(wire_sft121a_in[2:2]),
	.out(wire_sft121a_out[2:2]));
	assign
		wire_sft121a_in = {w276w, {dffe113, dffe109}};
	soft   sft122a_0
	( 
	.in(wire_sft122a_in[0:0]),
	.out(wire_sft122a_out[0:0]));
	soft   sft122a_1
	( 
	.in(wire_sft122a_in[1:1]),
	.out(wire_sft122a_out[1:1]));
	soft   sft122a_2
	( 
	.in(wire_sft122a_in[2:2]),
	.out(wire_sft122a_out[2:2]));
	assign
		wire_sft122a_in = {w276w, {w276w, dffe110}};
	soft   sft123a_0
	( 
	.in(wire_sft123a_in[0:0]),
	.out(wire_sft123a_out[0:0]));
	soft   sft123a_1
	( 
	.in(wire_sft123a_in[1:1]),
	.out(wire_sft123a_out[1:1]));
	soft   sft123a_2
	( 
	.in(wire_sft123a_in[2:2]),
	.out(wire_sft123a_out[2:2]));
	assign
		wire_sft123a_in = {w276w, {w276w, dffe111}};
	soft   sft124a_0
	( 
	.in(wire_sft124a_in[0:0]),
	.out(wire_sft124a_out[0:0]));
	soft   sft124a_1
	( 
	.in(wire_sft124a_in[1:1]),
	.out(wire_sft124a_out[1:1]));
	soft   sft124a_2
	( 
	.in(wire_sft124a_in[2:2]),
	.out(wire_sft124a_out[2:2]));
	assign
		wire_sft124a_in = wire_add120_result;
	soft   sft12a_0
	( 
	.in(wire_sft12a_in[0:0]),
	.out(wire_sft12a_out[0:0]));
	soft   sft12a_1
	( 
	.in(wire_sft12a_in[1:1]),
	.out(wire_sft12a_out[1:1]));
	assign
		wire_sft12a_in = {w30w, w21w[0]};
	soft   sft137a_0
	( 
	.in(wire_sft137a_in[0:0]),
	.out(wire_sft137a_out[0:0]));
	soft   sft137a_1
	( 
	.in(wire_sft137a_in[1:1]),
	.out(wire_sft137a_out[1:1]));
	assign
		wire_sft137a_in = {w325w, w319w[0]};
	soft   sft138a_0
	( 
	.in(wire_sft138a_in[0:0]),
	.out(wire_sft138a_out[0:0]));
	soft   sft138a_1
	( 
	.in(wire_sft138a_in[1:1]),
	.out(wire_sft138a_out[1:1]));
	assign
		wire_sft138a_in = {w325w, w316w[0]};
	soft   sft139a_0
	( 
	.in(wire_sft139a_in[0:0]),
	.out(wire_sft139a_out[0:0]));
	soft   sft139a_1
	( 
	.in(wire_sft139a_in[1:1]),
	.out(wire_sft139a_out[1:1]));
	assign
		wire_sft139a_in = {2{w325w}};
	soft   sft13a_0
	( 
	.in(wire_sft13a_in[0:0]),
	.out(wire_sft13a_out[0:0]));
	soft   sft13a_1
	( 
	.in(wire_sft13a_in[1:1]),
	.out(wire_sft13a_out[1:1]));
	assign
		wire_sft13a_in = {2{w30w}};
	soft   sft140a_0
	( 
	.in(wire_sft140a_in[0:0]),
	.out(wire_sft140a_out[0:0]));
	soft   sft140a_1
	( 
	.in(wire_sft140a_in[1:1]),
	.out(wire_sft140a_out[1:1]));
	assign
		wire_sft140a_in = wire_add136_result;
	soft   sft142a_0
	( 
	.in(wire_sft142a_in[0:0]),
	.out(wire_sft142a_out[0:0]));
	soft   sft142a_1
	( 
	.in(wire_sft142a_in[1:1]),
	.out(wire_sft142a_out[1:1]));
	soft   sft142a_2
	( 
	.in(wire_sft142a_in[2:2]),
	.out(wire_sft142a_out[2:2]));
	assign
		wire_sft142a_in = {w325w, {dffe134, dffe130}};
	soft   sft143a_0
	( 
	.in(wire_sft143a_in[0:0]),
	.out(wire_sft143a_out[0:0]));
	soft   sft143a_1
	( 
	.in(wire_sft143a_in[1:1]),
	.out(wire_sft143a_out[1:1]));
	soft   sft143a_2
	( 
	.in(wire_sft143a_in[2:2]),
	.out(wire_sft143a_out[2:2]));
	assign
		wire_sft143a_in = {w325w, {w325w, dffe131}};
	soft   sft144a_0
	( 
	.in(wire_sft144a_in[0:0]),
	.out(wire_sft144a_out[0:0]));
	soft   sft144a_1
	( 
	.in(wire_sft144a_in[1:1]),
	.out(wire_sft144a_out[1:1]));
	soft   sft144a_2
	( 
	.in(wire_sft144a_in[2:2]),
	.out(wire_sft144a_out[2:2]));
	assign
		wire_sft144a_in = {w325w, {w325w, dffe132}};
	soft   sft145a_0
	( 
	.in(wire_sft145a_in[0:0]),
	.out(wire_sft145a_out[0:0]));
	soft   sft145a_1
	( 
	.in(wire_sft145a_in[1:1]),
	.out(wire_sft145a_out[1:1]));
	soft   sft145a_2
	( 
	.in(wire_sft145a_in[2:2]),
	.out(wire_sft145a_out[2:2]));
	assign
		wire_sft145a_in = wire_add141_result;
	soft   sft14a_0
	( 
	.in(wire_sft14a_in[0:0]),
	.out(wire_sft14a_out[0:0]));
	soft   sft14a_1
	( 
	.in(wire_sft14a_in[1:1]),
	.out(wire_sft14a_out[1:1]));
	assign
		wire_sft14a_in = wire_add10_result;
	soft   sft158a_0
	( 
	.in(wire_sft158a_in[0:0]),
	.out(wire_sft158a_out[0:0]));
	soft   sft158a_1
	( 
	.in(wire_sft158a_in[1:1]),
	.out(wire_sft158a_out[1:1]));
	assign
		wire_sft158a_in = {w374w, w368w[0]};
	soft   sft159a_0
	( 
	.in(wire_sft159a_in[0:0]),
	.out(wire_sft159a_out[0:0]));
	soft   sft159a_1
	( 
	.in(wire_sft159a_in[1:1]),
	.out(wire_sft159a_out[1:1]));
	assign
		wire_sft159a_in = {w374w, w365w[0]};
	soft   sft160a_0
	( 
	.in(wire_sft160a_in[0:0]),
	.out(wire_sft160a_out[0:0]));
	soft   sft160a_1
	( 
	.in(wire_sft160a_in[1:1]),
	.out(wire_sft160a_out[1:1]));
	assign
		wire_sft160a_in = {2{w374w}};
	soft   sft161a_0
	( 
	.in(wire_sft161a_in[0:0]),
	.out(wire_sft161a_out[0:0]));
	soft   sft161a_1
	( 
	.in(wire_sft161a_in[1:1]),
	.out(wire_sft161a_out[1:1]));
	assign
		wire_sft161a_in = wire_add157_result;
	soft   sft163a_0
	( 
	.in(wire_sft163a_in[0:0]),
	.out(wire_sft163a_out[0:0]));
	soft   sft163a_1
	( 
	.in(wire_sft163a_in[1:1]),
	.out(wire_sft163a_out[1:1]));
	soft   sft163a_2
	( 
	.in(wire_sft163a_in[2:2]),
	.out(wire_sft163a_out[2:2]));
	assign
		wire_sft163a_in = {w374w, {dffe155, dffe151}};
	soft   sft164a_0
	( 
	.in(wire_sft164a_in[0:0]),
	.out(wire_sft164a_out[0:0]));
	soft   sft164a_1
	( 
	.in(wire_sft164a_in[1:1]),
	.out(wire_sft164a_out[1:1]));
	soft   sft164a_2
	( 
	.in(wire_sft164a_in[2:2]),
	.out(wire_sft164a_out[2:2]));
	assign
		wire_sft164a_in = {w374w, {w374w, dffe152}};
	soft   sft165a_0
	( 
	.in(wire_sft165a_in[0:0]),
	.out(wire_sft165a_out[0:0]));
	soft   sft165a_1
	( 
	.in(wire_sft165a_in[1:1]),
	.out(wire_sft165a_out[1:1]));
	soft   sft165a_2
	( 
	.in(wire_sft165a_in[2:2]),
	.out(wire_sft165a_out[2:2]));
	assign
		wire_sft165a_in = {w374w, {w374w, dffe153}};
	soft   sft166a_0
	( 
	.in(wire_sft166a_in[0:0]),
	.out(wire_sft166a_out[0:0]));
	soft   sft166a_1
	( 
	.in(wire_sft166a_in[1:1]),
	.out(wire_sft166a_out[1:1]));
	soft   sft166a_2
	( 
	.in(wire_sft166a_in[2:2]),
	.out(wire_sft166a_out[2:2]));
	assign
		wire_sft166a_in = wire_add162_result;
	soft   sft16a_0
	( 
	.in(wire_sft16a_in[0:0]),
	.out(wire_sft16a_out[0:0]));
	soft   sft16a_1
	( 
	.in(wire_sft16a_in[1:1]),
	.out(wire_sft16a_out[1:1]));
	soft   sft16a_2
	( 
	.in(wire_sft16a_in[2:2]),
	.out(wire_sft16a_out[2:2]));
	assign
		wire_sft16a_in = {w30w, {dffe8, dffe4}};
	soft   sft179a_0
	( 
	.in(wire_sft179a_in[0:0]),
	.out(wire_sft179a_out[0:0]));
	soft   sft179a_1
	( 
	.in(wire_sft179a_in[1:1]),
	.out(wire_sft179a_out[1:1]));
	assign
		wire_sft179a_in = {w423w, w417w[0]};
	soft   sft17a_0
	( 
	.in(wire_sft17a_in[0:0]),
	.out(wire_sft17a_out[0:0]));
	soft   sft17a_1
	( 
	.in(wire_sft17a_in[1:1]),
	.out(wire_sft17a_out[1:1]));
	soft   sft17a_2
	( 
	.in(wire_sft17a_in[2:2]),
	.out(wire_sft17a_out[2:2]));
	assign
		wire_sft17a_in = {w30w, {w30w, dffe5}};
	soft   sft180a_0
	( 
	.in(wire_sft180a_in[0:0]),
	.out(wire_sft180a_out[0:0]));
	soft   sft180a_1
	( 
	.in(wire_sft180a_in[1:1]),
	.out(wire_sft180a_out[1:1]));
	assign
		wire_sft180a_in = {w423w, w414w[0]};
	soft   sft181a_0
	( 
	.in(wire_sft181a_in[0:0]),
	.out(wire_sft181a_out[0:0]));
	soft   sft181a_1
	( 
	.in(wire_sft181a_in[1:1]),
	.out(wire_sft181a_out[1:1]));
	assign
		wire_sft181a_in = {2{w423w}};
	soft   sft182a_0
	( 
	.in(wire_sft182a_in[0:0]),
	.out(wire_sft182a_out[0:0]));
	soft   sft182a_1
	( 
	.in(wire_sft182a_in[1:1]),
	.out(wire_sft182a_out[1:1]));
	assign
		wire_sft182a_in = wire_add178_result;
	soft   sft184a_0
	( 
	.in(wire_sft184a_in[0:0]),
	.out(wire_sft184a_out[0:0]));
	soft   sft184a_1
	( 
	.in(wire_sft184a_in[1:1]),
	.out(wire_sft184a_out[1:1]));
	soft   sft184a_2
	( 
	.in(wire_sft184a_in[2:2]),
	.out(wire_sft184a_out[2:2]));
	assign
		wire_sft184a_in = {w423w, {dffe176, dffe172}};
	soft   sft185a_0
	( 
	.in(wire_sft185a_in[0:0]),
	.out(wire_sft185a_out[0:0]));
	soft   sft185a_1
	( 
	.in(wire_sft185a_in[1:1]),
	.out(wire_sft185a_out[1:1]));
	soft   sft185a_2
	( 
	.in(wire_sft185a_in[2:2]),
	.out(wire_sft185a_out[2:2]));
	assign
		wire_sft185a_in = {w423w, {w423w, dffe173}};
	soft   sft186a_0
	( 
	.in(wire_sft186a_in[0:0]),
	.out(wire_sft186a_out[0:0]));
	soft   sft186a_1
	( 
	.in(wire_sft186a_in[1:1]),
	.out(wire_sft186a_out[1:1]));
	soft   sft186a_2
	( 
	.in(wire_sft186a_in[2:2]),
	.out(wire_sft186a_out[2:2]));
	assign
		wire_sft186a_in = {w423w, {w423w, dffe174}};
	soft   sft187a_0
	( 
	.in(wire_sft187a_in[0:0]),
	.out(wire_sft187a_out[0:0]));
	soft   sft187a_1
	( 
	.in(wire_sft187a_in[1:1]),
	.out(wire_sft187a_out[1:1]));
	soft   sft187a_2
	( 
	.in(wire_sft187a_in[2:2]),
	.out(wire_sft187a_out[2:2]));
	assign
		wire_sft187a_in = wire_add183_result;
	soft   sft18a_0
	( 
	.in(wire_sft18a_in[0:0]),
	.out(wire_sft18a_out[0:0]));
	soft   sft18a_1
	( 
	.in(wire_sft18a_in[1:1]),
	.out(wire_sft18a_out[1:1]));
	soft   sft18a_2
	( 
	.in(wire_sft18a_in[2:2]),
	.out(wire_sft18a_out[2:2]));
	assign
		wire_sft18a_in = {w30w, {w30w, dffe6}};
	soft   sft19a_0
	( 
	.in(wire_sft19a_in[0:0]),
	.out(wire_sft19a_out[0:0]));
	soft   sft19a_1
	( 
	.in(wire_sft19a_in[1:1]),
	.out(wire_sft19a_out[1:1]));
	soft   sft19a_2
	( 
	.in(wire_sft19a_in[2:2]),
	.out(wire_sft19a_out[2:2]));
	assign
		wire_sft19a_in = wire_add15_result;
	soft   sft32a_0
	( 
	.in(wire_sft32a_in[0:0]),
	.out(wire_sft32a_out[0:0]));
	soft   sft32a_1
	( 
	.in(wire_sft32a_in[1:1]),
	.out(wire_sft32a_out[1:1]));
	assign
		wire_sft32a_in = {w80w, w74w[0]};
	soft   sft33a_0
	( 
	.in(wire_sft33a_in[0:0]),
	.out(wire_sft33a_out[0:0]));
	soft   sft33a_1
	( 
	.in(wire_sft33a_in[1:1]),
	.out(wire_sft33a_out[1:1]));
	assign
		wire_sft33a_in = {w80w, w71w[0]};
	soft   sft34a_0
	( 
	.in(wire_sft34a_in[0:0]),
	.out(wire_sft34a_out[0:0]));
	soft   sft34a_1
	( 
	.in(wire_sft34a_in[1:1]),
	.out(wire_sft34a_out[1:1]));
	assign
		wire_sft34a_in = {2{w80w}};
	soft   sft35a_0
	( 
	.in(wire_sft35a_in[0:0]),
	.out(wire_sft35a_out[0:0]));
	soft   sft35a_1
	( 
	.in(wire_sft35a_in[1:1]),
	.out(wire_sft35a_out[1:1]));
	assign
		wire_sft35a_in = wire_add31_result;
	soft   sft37a_0
	( 
	.in(wire_sft37a_in[0:0]),
	.out(wire_sft37a_out[0:0]));
	soft   sft37a_1
	( 
	.in(wire_sft37a_in[1:1]),
	.out(wire_sft37a_out[1:1]));
	soft   sft37a_2
	( 
	.in(wire_sft37a_in[2:2]),
	.out(wire_sft37a_out[2:2]));
	assign
		wire_sft37a_in = {w80w, {dffe29, dffe25}};
	soft   sft38a_0
	( 
	.in(wire_sft38a_in[0:0]),
	.out(wire_sft38a_out[0:0]));
	soft   sft38a_1
	( 
	.in(wire_sft38a_in[1:1]),
	.out(wire_sft38a_out[1:1]));
	soft   sft38a_2
	( 
	.in(wire_sft38a_in[2:2]),
	.out(wire_sft38a_out[2:2]));
	assign
		wire_sft38a_in = {w80w, {w80w, dffe26}};
	soft   sft39a_0
	( 
	.in(wire_sft39a_in[0:0]),
	.out(wire_sft39a_out[0:0]));
	soft   sft39a_1
	( 
	.in(wire_sft39a_in[1:1]),
	.out(wire_sft39a_out[1:1]));
	soft   sft39a_2
	( 
	.in(wire_sft39a_in[2:2]),
	.out(wire_sft39a_out[2:2]));
	assign
		wire_sft39a_in = {w80w, {w80w, dffe27}};
	soft   sft40a_0
	( 
	.in(wire_sft40a_in[0:0]),
	.out(wire_sft40a_out[0:0]));
	soft   sft40a_1
	( 
	.in(wire_sft40a_in[1:1]),
	.out(wire_sft40a_out[1:1]));
	soft   sft40a_2
	( 
	.in(wire_sft40a_in[2:2]),
	.out(wire_sft40a_out[2:2]));
	assign
		wire_sft40a_in = wire_add36_result;
	soft   sft53a_0
	( 
	.in(wire_sft53a_in[0:0]),
	.out(wire_sft53a_out[0:0]));
	soft   sft53a_1
	( 
	.in(wire_sft53a_in[1:1]),
	.out(wire_sft53a_out[1:1]));
	assign
		wire_sft53a_in = {w129w, w123w[0]};
	soft   sft54a_0
	( 
	.in(wire_sft54a_in[0:0]),
	.out(wire_sft54a_out[0:0]));
	soft   sft54a_1
	( 
	.in(wire_sft54a_in[1:1]),
	.out(wire_sft54a_out[1:1]));
	assign
		wire_sft54a_in = {w129w, w120w[0]};
	soft   sft55a_0
	( 
	.in(wire_sft55a_in[0:0]),
	.out(wire_sft55a_out[0:0]));
	soft   sft55a_1
	( 
	.in(wire_sft55a_in[1:1]),
	.out(wire_sft55a_out[1:1]));
	assign
		wire_sft55a_in = {2{w129w}};
	soft   sft56a_0
	( 
	.in(wire_sft56a_in[0:0]),
	.out(wire_sft56a_out[0:0]));
	soft   sft56a_1
	( 
	.in(wire_sft56a_in[1:1]),
	.out(wire_sft56a_out[1:1]));
	assign
		wire_sft56a_in = wire_add52_result;
	soft   sft58a_0
	( 
	.in(wire_sft58a_in[0:0]),
	.out(wire_sft58a_out[0:0]));
	soft   sft58a_1
	( 
	.in(wire_sft58a_in[1:1]),
	.out(wire_sft58a_out[1:1]));
	soft   sft58a_2
	( 
	.in(wire_sft58a_in[2:2]),
	.out(wire_sft58a_out[2:2]));
	assign
		wire_sft58a_in = {w129w, {dffe50, dffe46}};
	soft   sft59a_0
	( 
	.in(wire_sft59a_in[0:0]),
	.out(wire_sft59a_out[0:0]));
	soft   sft59a_1
	( 
	.in(wire_sft59a_in[1:1]),
	.out(wire_sft59a_out[1:1]));
	soft   sft59a_2
	( 
	.in(wire_sft59a_in[2:2]),
	.out(wire_sft59a_out[2:2]));
	assign
		wire_sft59a_in = {w129w, {w129w, dffe47}};
	soft   sft60a_0
	( 
	.in(wire_sft60a_in[0:0]),
	.out(wire_sft60a_out[0:0]));
	soft   sft60a_1
	( 
	.in(wire_sft60a_in[1:1]),
	.out(wire_sft60a_out[1:1]));
	soft   sft60a_2
	( 
	.in(wire_sft60a_in[2:2]),
	.out(wire_sft60a_out[2:2]));
	assign
		wire_sft60a_in = {w129w, {w129w, dffe48}};
	soft   sft61a_0
	( 
	.in(wire_sft61a_in[0:0]),
	.out(wire_sft61a_out[0:0]));
	soft   sft61a_1
	( 
	.in(wire_sft61a_in[1:1]),
	.out(wire_sft61a_out[1:1]));
	soft   sft61a_2
	( 
	.in(wire_sft61a_in[2:2]),
	.out(wire_sft61a_out[2:2]));
	assign
		wire_sft61a_in = wire_add57_result;
	soft   sft74a_0
	( 
	.in(wire_sft74a_in[0:0]),
	.out(wire_sft74a_out[0:0]));
	soft   sft74a_1
	( 
	.in(wire_sft74a_in[1:1]),
	.out(wire_sft74a_out[1:1]));
	assign
		wire_sft74a_in = {w178w, w172w[0]};
	soft   sft75a_0
	( 
	.in(wire_sft75a_in[0:0]),
	.out(wire_sft75a_out[0:0]));
	soft   sft75a_1
	( 
	.in(wire_sft75a_in[1:1]),
	.out(wire_sft75a_out[1:1]));
	assign
		wire_sft75a_in = {w178w, w169w[0]};
	soft   sft76a_0
	( 
	.in(wire_sft76a_in[0:0]),
	.out(wire_sft76a_out[0:0]));
	soft   sft76a_1
	( 
	.in(wire_sft76a_in[1:1]),
	.out(wire_sft76a_out[1:1]));
	assign
		wire_sft76a_in = {2{w178w}};
	soft   sft77a_0
	( 
	.in(wire_sft77a_in[0:0]),
	.out(wire_sft77a_out[0:0]));
	soft   sft77a_1
	( 
	.in(wire_sft77a_in[1:1]),
	.out(wire_sft77a_out[1:1]));
	assign
		wire_sft77a_in = wire_add73_result;
	soft   sft79a_0
	( 
	.in(wire_sft79a_in[0:0]),
	.out(wire_sft79a_out[0:0]));
	soft   sft79a_1
	( 
	.in(wire_sft79a_in[1:1]),
	.out(wire_sft79a_out[1:1]));
	soft   sft79a_2
	( 
	.in(wire_sft79a_in[2:2]),
	.out(wire_sft79a_out[2:2]));
	assign
		wire_sft79a_in = {w178w, {dffe71, dffe67}};
	soft   sft80a_0
	( 
	.in(wire_sft80a_in[0:0]),
	.out(wire_sft80a_out[0:0]));
	soft   sft80a_1
	( 
	.in(wire_sft80a_in[1:1]),
	.out(wire_sft80a_out[1:1]));
	soft   sft80a_2
	( 
	.in(wire_sft80a_in[2:2]),
	.out(wire_sft80a_out[2:2]));
	assign
		wire_sft80a_in = {w178w, {w178w, dffe68}};
	soft   sft81a_0
	( 
	.in(wire_sft81a_in[0:0]),
	.out(wire_sft81a_out[0:0]));
	soft   sft81a_1
	( 
	.in(wire_sft81a_in[1:1]),
	.out(wire_sft81a_out[1:1]));
	soft   sft81a_2
	( 
	.in(wire_sft81a_in[2:2]),
	.out(wire_sft81a_out[2:2]));
	assign
		wire_sft81a_in = {w178w, {w178w, dffe69}};
	soft   sft82a_0
	( 
	.in(wire_sft82a_in[0:0]),
	.out(wire_sft82a_out[0:0]));
	soft   sft82a_1
	( 
	.in(wire_sft82a_in[1:1]),
	.out(wire_sft82a_out[1:1]));
	soft   sft82a_2
	( 
	.in(wire_sft82a_in[2:2]),
	.out(wire_sft82a_out[2:2]));
	assign
		wire_sft82a_in = wire_add78_result;
	soft   sft95a_0
	( 
	.in(wire_sft95a_in[0:0]),
	.out(wire_sft95a_out[0:0]));
	soft   sft95a_1
	( 
	.in(wire_sft95a_in[1:1]),
	.out(wire_sft95a_out[1:1]));
	assign
		wire_sft95a_in = {w227w, w221w[0]};
	soft   sft96a_0
	( 
	.in(wire_sft96a_in[0:0]),
	.out(wire_sft96a_out[0:0]));
	soft   sft96a_1
	( 
	.in(wire_sft96a_in[1:1]),
	.out(wire_sft96a_out[1:1]));
	assign
		wire_sft96a_in = {w227w, w218w[0]};
	soft   sft97a_0
	( 
	.in(wire_sft97a_in[0:0]),
	.out(wire_sft97a_out[0:0]));
	soft   sft97a_1
	( 
	.in(wire_sft97a_in[1:1]),
	.out(wire_sft97a_out[1:1]));
	assign
		wire_sft97a_in = {2{w227w}};
	soft   sft98a_0
	( 
	.in(wire_sft98a_in[0:0]),
	.out(wire_sft98a_out[0:0]));
	soft   sft98a_1
	( 
	.in(wire_sft98a_in[1:1]),
	.out(wire_sft98a_out[1:1]));
	assign
		wire_sft98a_in = wire_add94_result;
	arriaii_lvds_receiver   rx_0
	( 
	.bitslip(wire_rx_bitslip[0:0]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[0:0]),
	.datain(wire_rx_datain[0:0]),
	.dataout(wire_rx_dataout[3:0]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[0:0]),
	.dpaswitch(wire_rx_dpaswitch[0:0]),
	.enable0(wire_rx_enable0[0:0]),
	.fiforeset(wire_rx_fiforeset[0:0]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_0.channel_width = 4,
		rx_0.data_align_rollover = 4,
		rx_0.dpa_initial_phase_value = 0,
		rx_0.dpa_output_clock_phase_shift = 0,
		rx_0.enable_dpa = "on",
		rx_0.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_0.enable_dpa_initial_phase_selection = "ON",
		rx_0.is_negative_ppm_drift = "OFF",
		rx_0.net_ppm_variation = 0,
		rx_0.reset_fifo_at_first_lock = "off",
		rx_0.rx_input_path_delay_engineering_bits = 3,
		rx_0.x_on_bitslip = "on",
		rx_0.lpm_type = "arriaii_lvds_receiver";
	arriaii_lvds_receiver   rx_1
	( 
	.bitslip(wire_rx_bitslip[1:1]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[1:1]),
	.datain(wire_rx_datain[1:1]),
	.dataout(wire_rx_dataout[7:4]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[1:1]),
	.dpaswitch(wire_rx_dpaswitch[1:1]),
	.enable0(wire_rx_enable0[1:1]),
	.fiforeset(wire_rx_fiforeset[1:1]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_1.channel_width = 4,
		rx_1.data_align_rollover = 4,
		rx_1.dpa_initial_phase_value = 0,
		rx_1.dpa_output_clock_phase_shift = 0,
		rx_1.enable_dpa = "on",
		rx_1.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_1.enable_dpa_initial_phase_selection = "ON",
		rx_1.is_negative_ppm_drift = "OFF",
		rx_1.net_ppm_variation = 0,
		rx_1.reset_fifo_at_first_lock = "off",
		rx_1.rx_input_path_delay_engineering_bits = 3,
		rx_1.x_on_bitslip = "on",
		rx_1.lpm_type = "arriaii_lvds_receiver";
	arriaii_lvds_receiver   rx_2
	( 
	.bitslip(wire_rx_bitslip[2:2]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[2:2]),
	.datain(wire_rx_datain[2:2]),
	.dataout(wire_rx_dataout[11:8]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[2:2]),
	.dpaswitch(wire_rx_dpaswitch[2:2]),
	.enable0(wire_rx_enable0[2:2]),
	.fiforeset(wire_rx_fiforeset[2:2]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_2.channel_width = 4,
		rx_2.data_align_rollover = 4,
		rx_2.dpa_initial_phase_value = 0,
		rx_2.dpa_output_clock_phase_shift = 0,
		rx_2.enable_dpa = "on",
		rx_2.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_2.enable_dpa_initial_phase_selection = "ON",
		rx_2.is_negative_ppm_drift = "OFF",
		rx_2.net_ppm_variation = 0,
		rx_2.reset_fifo_at_first_lock = "off",
		rx_2.rx_input_path_delay_engineering_bits = 3,
		rx_2.x_on_bitslip = "on",
		rx_2.lpm_type = "arriaii_lvds_receiver";
	arriaii_lvds_receiver   rx_3
	( 
	.bitslip(wire_rx_bitslip[3:3]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[3:3]),
	.datain(wire_rx_datain[3:3]),
	.dataout(wire_rx_dataout[15:12]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[3:3]),
	.dpaswitch(wire_rx_dpaswitch[3:3]),
	.enable0(wire_rx_enable0[3:3]),
	.fiforeset(wire_rx_fiforeset[3:3]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_3.channel_width = 4,
		rx_3.data_align_rollover = 4,
		rx_3.dpa_initial_phase_value = 0,
		rx_3.dpa_output_clock_phase_shift = 0,
		rx_3.enable_dpa = "on",
		rx_3.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_3.enable_dpa_initial_phase_selection = "ON",
		rx_3.is_negative_ppm_drift = "OFF",
		rx_3.net_ppm_variation = 0,
		rx_3.reset_fifo_at_first_lock = "off",
		rx_3.rx_input_path_delay_engineering_bits = 3,
		rx_3.x_on_bitslip = "on",
		rx_3.lpm_type = "arriaii_lvds_receiver";
	arriaii_lvds_receiver   rx_4
	( 
	.bitslip(wire_rx_bitslip[4:4]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[4:4]),
	.datain(wire_rx_datain[4:4]),
	.dataout(wire_rx_dataout[19:16]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[4:4]),
	.dpaswitch(wire_rx_dpaswitch[4:4]),
	.enable0(wire_rx_enable0[4:4]),
	.fiforeset(wire_rx_fiforeset[4:4]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_4.channel_width = 4,
		rx_4.data_align_rollover = 4,
		rx_4.dpa_initial_phase_value = 0,
		rx_4.dpa_output_clock_phase_shift = 0,
		rx_4.enable_dpa = "on",
		rx_4.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_4.enable_dpa_initial_phase_selection = "ON",
		rx_4.is_negative_ppm_drift = "OFF",
		rx_4.net_ppm_variation = 0,
		rx_4.reset_fifo_at_first_lock = "off",
		rx_4.rx_input_path_delay_engineering_bits = 3,
		rx_4.x_on_bitslip = "on",
		rx_4.lpm_type = "arriaii_lvds_receiver";
	arriaii_lvds_receiver   rx_5
	( 
	.bitslip(wire_rx_bitslip[5:5]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[5:5]),
	.datain(wire_rx_datain[5:5]),
	.dataout(wire_rx_dataout[23:20]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[5:5]),
	.dpaswitch(wire_rx_dpaswitch[5:5]),
	.enable0(wire_rx_enable0[5:5]),
	.fiforeset(wire_rx_fiforeset[5:5]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_5.channel_width = 4,
		rx_5.data_align_rollover = 4,
		rx_5.dpa_initial_phase_value = 0,
		rx_5.dpa_output_clock_phase_shift = 0,
		rx_5.enable_dpa = "on",
		rx_5.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_5.enable_dpa_initial_phase_selection = "ON",
		rx_5.is_negative_ppm_drift = "OFF",
		rx_5.net_ppm_variation = 0,
		rx_5.reset_fifo_at_first_lock = "off",
		rx_5.rx_input_path_delay_engineering_bits = 3,
		rx_5.x_on_bitslip = "on",
		rx_5.lpm_type = "arriaii_lvds_receiver";
	arriaii_lvds_receiver   rx_6
	( 
	.bitslip(wire_rx_bitslip[6:6]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[6:6]),
	.datain(wire_rx_datain[6:6]),
	.dataout(wire_rx_dataout[27:24]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[6:6]),
	.dpaswitch(wire_rx_dpaswitch[6:6]),
	.enable0(wire_rx_enable0[6:6]),
	.fiforeset(wire_rx_fiforeset[6:6]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_6.channel_width = 4,
		rx_6.data_align_rollover = 4,
		rx_6.dpa_initial_phase_value = 0,
		rx_6.dpa_output_clock_phase_shift = 0,
		rx_6.enable_dpa = "on",
		rx_6.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_6.enable_dpa_initial_phase_selection = "ON",
		rx_6.is_negative_ppm_drift = "OFF",
		rx_6.net_ppm_variation = 0,
		rx_6.reset_fifo_at_first_lock = "off",
		rx_6.rx_input_path_delay_engineering_bits = 3,
		rx_6.x_on_bitslip = "on",
		rx_6.lpm_type = "arriaii_lvds_receiver";
	arriaii_lvds_receiver   rx_7
	( 
	.bitslip(wire_rx_bitslip[7:7]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[7:7]),
	.datain(wire_rx_datain[7:7]),
	.dataout(wire_rx_dataout[31:28]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[7:7]),
	.dpaswitch(wire_rx_dpaswitch[7:7]),
	.enable0(wire_rx_enable0[7:7]),
	.fiforeset(wire_rx_fiforeset[7:7]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_7.channel_width = 4,
		rx_7.data_align_rollover = 4,
		rx_7.dpa_initial_phase_value = 0,
		rx_7.dpa_output_clock_phase_shift = 0,
		rx_7.enable_dpa = "on",
		rx_7.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_7.enable_dpa_initial_phase_selection = "ON",
		rx_7.is_negative_ppm_drift = "OFF",
		rx_7.net_ppm_variation = 0,
		rx_7.reset_fifo_at_first_lock = "off",
		rx_7.rx_input_path_delay_engineering_bits = 3,
		rx_7.x_on_bitslip = "on",
		rx_7.lpm_type = "arriaii_lvds_receiver";
	arriaii_lvds_receiver   rx_8
	( 
	.bitslip(wire_rx_bitslip[8:8]),
	.bitslipmax(),
	.clk0(wire_rx_clk0[8:8]),
	.datain(wire_rx_datain[8:8]),
	.dataout(wire_rx_dataout[35:32]),
	.divfwdclk(),
	.dpaclkout(),
	.dpalock(),
	.dpareset(wire_rx_dpareset[8:8]),
	.dpaswitch(wire_rx_dpaswitch[8:8]),
	.enable0(wire_rx_enable0[8:8]),
	.fiforeset(wire_rx_fiforeset[8:8]),
	.postdpaserialdataout(),
	.serialdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipreset(1'b0),
	.dpahold(1'b0),
	.serialfbk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		rx_8.channel_width = 4,
		rx_8.data_align_rollover = 4,
		rx_8.dpa_initial_phase_value = 0,
		rx_8.dpa_output_clock_phase_shift = 0,
		rx_8.enable_dpa = "on",
		rx_8.enable_dpa_align_to_rising_edge_only = "OFF",
		rx_8.enable_dpa_initial_phase_selection = "ON",
		rx_8.is_negative_ppm_drift = "OFF",
		rx_8.net_ppm_variation = 0,
		rx_8.reset_fifo_at_first_lock = "off",
		rx_8.rx_input_path_delay_engineering_bits = 3,
		rx_8.x_on_bitslip = "on",
		rx_8.lpm_type = "arriaii_lvds_receiver";
	assign
		wire_rx_bitslip = rx_channel_data_align,
		wire_rx_clk0 = {9{wire_pll_clk[0]}},
		wire_rx_datain = rx_in,
		wire_rx_dpareset = rx_reset,
		wire_rx_dpaswitch = dpaswitch_wire,
		wire_rx_enable0 = {9{wire_pll_clk[1]}},
		wire_rx_fiforeset = (dpa_lock_fifo_reset | rx_fifo_reset);
	arriaii_pll   pll
	( 
	.activeclock(),
	.areset(pll_areset),
	.clk(wire_pll_clk),
	.clkbad(),
	.fbin(wire_pll_fbout),
	.fbout(wire_pll_fbout),
	.inclk({{1{1'b0}}, rx_inclock}),
	.locked(wire_pll_locked),
	.phasedone(),
	.scandataout(),
	.scandone(),
	.vcooverrange(),
	.vcounderrange()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.clkswitch(1'b0),
	.configupdate(1'b0),
	.pfdena(1'b1),
	.phasecounterselect({4{1'b0}}),
	.phasestep(1'b0),
	.phaseupdown(1'b0),
	.scanclk(1'b0),
	.scanclkena(1'b1),
	.scandata(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		pll.clk0_divide_by = 1,
		pll.clk0_multiply_by = 4,
		pll.clk0_phase_shift = "977",
		pll.clk1_divide_by = 4,
		pll.clk1_duty_cycle = 25,
		pll.clk1_multiply_by = 4,
		pll.clk1_phase_shift = "5857",
		pll.clk2_divide_by = 4,
		pll.clk2_multiply_by = 4,
		pll.clk2_phase_shift = "977",
		pll.compensate_clock = "lvdsclk",
		pll.dpa_divide_by = 1,
		pll.dpa_multiply_by = 4,
		pll.inclk0_input_frequency = 7812,
		pll.operation_mode = "source_synchronous",
		pll.pll_type = "fast",
		pll.lpm_type = "arriaii_pll";
	assign
		dpa_lock_fifo_reset = {(((~ lock_state_mc206a[0]) & lock_state_mc206a[1]) & (int_dpa_locked_out_wire[8] ^ lock_out_reg_dly207a)), (((~ lock_state_mc204a[0]) & lock_state_mc204a[1]) & (int_dpa_locked_out_wire[7] ^ lock_out_reg_dly205a)), (((~ lock_state_mc202a[0]) & lock_state_mc202a[1]) & (int_dpa_locked_out_wire[6] ^ lock_out_reg_dly203a)), (((~ lock_state_mc200a[0]) & lock_state_mc200a[1]) & (int_dpa_locked_out_wire[5] ^ lock_out_reg_dly201a)), (((~ lock_state_mc198a[0]) & lock_state_mc198a[1]) & (int_dpa_locked_out_wire[4] ^ lock_out_reg_dly199a)), (((~ lock_state_mc196a[0]) & lock_state_mc196a[1]) & (int_dpa_locked_out_wire[3] ^ lock_out_reg_dly197a)), (((~ lock_state_mc194a[0]) & lock_state_mc194a[1]) & (int_dpa_locked_out_wire[2] ^ lock_out_reg_dly195a)), (((~ lock_state_mc192a[0]) & lock_state_mc192a[1]) & (int_dpa_locked_out_wire[1] ^ lock_out_reg_dly193a)), (((~ lock_state_mc190a[0]) & lock_state_mc190a[1]) & (int_dpa_locked_out_wire[0] ^ lock_out_reg_dly191a))},
		dpa_locked_out_wire = {((lock_state_mc206a[0] & lock_state_mc206a[1]) & lock_out_reg_dly207a), ((lock_state_mc204a[0] & lock_state_mc204a[1]) & lock_out_reg_dly205a), ((lock_state_mc202a[0] & lock_state_mc202a[1]) & lock_out_reg_dly203a), ((lock_state_mc200a[0] & lock_state_mc200a[1]) & lock_out_reg_dly201a), ((lock_state_mc198a[0] & lock_state_mc198a[1]) & lock_out_reg_dly199a), ((lock_state_mc196a[0] & lock_state_mc196a[1]) & lock_out_reg_dly197a), ((lock_state_mc194a[0] & lock_state_mc194a[1]) & lock_out_reg_dly195a), ((lock_state_mc192a[0] & lock_state_mc192a[1]) & lock_out_reg_dly193a), ((lock_state_mc190a[0] & lock_state_mc190a[1]) & lock_out_reg_dly191a)},
		dpa_locked_wire = dpa_locked_out_wire,
		dpaswitch_wire = {(~ ((~ lock_state_mc206a[0]) & (~ lock_state_mc206a[1]))), (~ ((~ lock_state_mc204a[0]) & (~ lock_state_mc204a[1]))), (~ ((~ lock_state_mc202a[0]) & (~ lock_state_mc202a[1]))), (~ ((~ lock_state_mc200a[0]) & (~ lock_state_mc200a[1]))), (~ ((~ lock_state_mc198a[0]) & (~ lock_state_mc198a[1]))), (~ ((~ lock_state_mc196a[0]) & (~ lock_state_mc196a[1]))), (~ ((~ lock_state_mc194a[0]) & (~ lock_state_mc194a[1]))), (~ ((~ lock_state_mc192a[0]) & (~ lock_state_mc192a[1]))), (~ ((~ lock_state_mc190a[0]) & (~ lock_state_mc190a[1])))},
		int_dpa_locked_out_wire = {lock_out_reg189a, lock_out_reg168a, lock_out_reg147a, lock_out_reg126a, lock_out_reg105a, lock_out_reg84a, lock_out_reg63a, lock_out_reg42a, lock_out_reg21a},
		int_pll_kick_reset = {(lock_state_mc206a[0] & (~ lock_state_mc206a[1])), (lock_state_mc204a[0] & (~ lock_state_mc204a[1])), (lock_state_mc202a[0] & (~ lock_state_mc202a[1])), (lock_state_mc200a[0] & (~ lock_state_mc200a[1])), (lock_state_mc198a[0] & (~ lock_state_mc198a[1])), (lock_state_mc196a[0] & (~ lock_state_mc196a[1])), (lock_state_mc194a[0] & (~ lock_state_mc194a[1])), (lock_state_mc192a[0] & (~ lock_state_mc192a[1])), (lock_state_mc190a[0] & (~ lock_state_mc190a[1]))},
		outclock = wire_rx_outclock_buf_outclk,
		pll_locked_out = (wire_pll_locked & pll_lock_sync),
		rx_dpa_locked = dpa_locked_wire,
		rx_locked = pll_locked_out,
		rx_out = rxreg,
		rx_out_wire = rxreg,
		rx_outclock = outclock,
		w102w = (rx_reset | {9{(~ pll_locked_out)}}),
		w112w = (extra_reg44a ^ pad_regr43a[3]),
		w116w = (pad_regr43a[1] ^ pad_regr43a[0]),
		w120w = (pad_regr43a[2] ^ pad_regr43a[1]),
		w123w = (pad_regr43a[3] ^ pad_regr43a[2]),
		w129w = 1'b0,
		w13w = (extra_reg2a ^ pad_regr1a[3]),
		w144w = {dffe51, dffe49, dffe45},
		w151w = (rx_reset | {9{(~ pll_locked_out)}}),
		w161w = (extra_reg65a ^ pad_regr64a[3]),
		w165w = (pad_regr64a[1] ^ pad_regr64a[0]),
		w169w = (pad_regr64a[2] ^ pad_regr64a[1]),
		w172w = (pad_regr64a[3] ^ pad_regr64a[2]),
		w178w = 1'b0,
		w17w = (pad_regr1a[1] ^ pad_regr1a[0]),
		w193w = {dffe72, dffe70, dffe66},
		w200w = (rx_reset | {9{(~ pll_locked_out)}}),
		w210w = (extra_reg86a ^ pad_regr85a[3]),
		w214w = (pad_regr85a[1] ^ pad_regr85a[0]),
		w218w = (pad_regr85a[2] ^ pad_regr85a[1]),
		w21w = (pad_regr1a[2] ^ pad_regr1a[1]),
		w221w = (pad_regr85a[3] ^ pad_regr85a[2]),
		w227w = 1'b0,
		w249w = (rx_reset | {9{(~ pll_locked_out)}}),
		w24w = (pad_regr1a[3] ^ pad_regr1a[2]),
		w259w = (extra_reg107a ^ pad_regr106a[3]),
		w263w = (pad_regr106a[1] ^ pad_regr106a[0]),
		w267w = (pad_regr106a[2] ^ pad_regr106a[1]),
		w270w = (pad_regr106a[3] ^ pad_regr106a[2]),
		w276w = 1'b0,
		w291w = {dffe114, dffe112, dffe108},
		w298w = (rx_reset | {9{(~ pll_locked_out)}}),
		w308w = (extra_reg128a ^ pad_regr127a[3]),
		w30w = 1'b0,
		w312w = (pad_regr127a[1] ^ pad_regr127a[0]),
		w316w = (pad_regr127a[2] ^ pad_regr127a[1]),
		w319w = (pad_regr127a[3] ^ pad_regr127a[2]),
		w325w = 1'b0,
		w340w = {dffe135, dffe133, dffe129},
		w347w = (rx_reset | {9{(~ pll_locked_out)}}),
		w357w = (extra_reg149a ^ pad_regr148a[3]),
		w361w = (pad_regr148a[1] ^ pad_regr148a[0]),
		w365w = (pad_regr148a[2] ^ pad_regr148a[1]),
		w368w = (pad_regr148a[3] ^ pad_regr148a[2]),
		w374w = 1'b0,
		w389w = {dffe156, dffe154, dffe150},
		w396w = (rx_reset | {9{(~ pll_locked_out)}}),
		w3w = (rx_reset | {9{(~ pll_locked_out)}}),
		w406w = (extra_reg170a ^ pad_regr169a[3]),
		w410w = (pad_regr169a[1] ^ pad_regr169a[0]),
		w414w = (pad_regr169a[2] ^ pad_regr169a[1]),
		w417w = (pad_regr169a[3] ^ pad_regr169a[2]),
		w423w = 1'b0,
		w438w = {dffe177, dffe175, dffe171},
		w445w = (rx_reset | {9{(~ pll_locked_out)}}),
		w45w = {dffe9, dffe7, dffe3},
		w482w = (rx_reset | {9{(~ pll_locked_out)}}),
		w494w = (rx_reset | {9{(~ pll_locked_out)}}),
		w529w = (rx_reset | {9{(~ pll_locked_out)}}),
		w539w = (rx_reset | {9{(~ pll_locked_out)}}),
		w53w = (rx_reset | {9{(~ pll_locked_out)}}),
		w574w = (rx_reset | {9{(~ pll_locked_out)}}),
		w584w = (rx_reset | {9{(~ pll_locked_out)}}),
		w619w = (rx_reset | {9{(~ pll_locked_out)}}),
		w629w = (rx_reset | {9{(~ pll_locked_out)}}),
		w63w = (extra_reg23a ^ pad_regr22a[3]),
		w664w = (rx_reset | {9{(~ pll_locked_out)}}),
		w674w = (rx_reset | {9{(~ pll_locked_out)}}),
		w67w = (pad_regr22a[1] ^ pad_regr22a[0]),
		w709w = (rx_reset | {9{(~ pll_locked_out)}}),
		w719w = (rx_reset | {9{(~ pll_locked_out)}}),
		w71w = (pad_regr22a[2] ^ pad_regr22a[1]),
		w74w = (pad_regr22a[3] ^ pad_regr22a[2]),
		w754w = (rx_reset | {9{(~ pll_locked_out)}}),
		w764w = (rx_reset | {9{(~ pll_locked_out)}}),
		w799w = (rx_reset | {9{(~ pll_locked_out)}}),
		w809w = (rx_reset | {9{(~ pll_locked_out)}}),
		w80w = 1'b0,
		w844w = (rx_reset | {9{(~ pll_locked_out)}}),
		w95w = {dffe30, dffe28, dffe24},
		w_sm_0448w = 1'b0,
		w_sm_0497w = 1'b0,
		w_sm_0542w = 1'b0,
		w_sm_0587w = 1'b0,
		w_sm_0632w = 1'b0,
		w_sm_0677w = 1'b0,
		w_sm_0722w = 1'b0,
		w_sm_0767w = 1'b0,
		w_sm_0812w = 1'b0;
endmodule //linki_v10_lvds_rx
//VALID FILE
