// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb 

// ============================================================
// File Name: trans.v
// Megafunction Name(s):
// 			alt4gxb
//
// Simulation Library Files(s):
// 			arriaii_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 153 11/29/2010 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Arria II GX" effective_data_rate="3125 Mbps" enable_lc_tx_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="156.25 MHz" intended_device_speed_grade="5" intended_device_variant="ANY" loopback_mode="none" number_of_channels=2 number_of_quads=1 operation_mode="tx" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="basic" reconfig_dprio_mode=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_channel_bonding="x4" tx_channel_width=16 tx_clkout_width=2 tx_common_mode="0.65v" tx_data_rate=3125 tx_data_rate_remainder=0 tx_datapath_low_latency_mode="false" tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_flip_tx_in="false" tx_force_disparity_mode="false" tx_pll_bandwidth_type="auto" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=6400 tx_pll_m_divider=10 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout pll_inclk pll_locked tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset
//VERSION_BEGIN 10.1 cbx_alt4gxb 2010:11:29:21:11:45:SJ cbx_mgl 2010:11:29:21:14:14:SJ cbx_tgx 2010:11:29:21:11:44:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463


//synthesis_resources = arriaii_hssi_calibration_block 1 arriaii_hssi_clock_divider 1 arriaii_hssi_cmu 1 arriaii_hssi_pll 1 arriaii_hssi_tx_pcs 2 arriaii_hssi_tx_pma 2 reg 3 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  trans_alt4gxb
	( 
	cal_blk_clk,
	coreclkout,
	pll_inclk,
	pll_locked,
	tx_clkout,
	tx_ctrlenable,
	tx_datain,
	tx_dataout,
	tx_digitalreset) ;
	input   cal_blk_clk;
	output   [0:0]  coreclkout;
	input   pll_inclk;
	output   [0:0]  pll_locked;
	output   [1:0]  tx_clkout;
	input   [3:0]  tx_ctrlenable;
	input   [31:0]  tx_datain;
	output   [1:0]  tx_dataout;
	input   [0:0]  tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   cal_blk_clk;
	tri0   pll_inclk;
	tri0   [3:0]  tx_ctrlenable;
	tri0   [31:0]  tx_datain;
	tri0   [0:0]  tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif


	parameter	starting_channel_number = 0;


	wire	[2:0]	wire_tx_digitalreset_reg0c_d;
	reg	[2:0]	tx_digitalreset_reg0c;
	wire	[2:0]	wire_tx_digitalreset_reg0c_clk;
	wire  wire_cal_blk0_nonusertocmu;
	wire  [1:0]   wire_central_clk_div0_analogfastrefclkout;
	wire  [1:0]   wire_central_clk_div0_analogrefclkout;
	wire  wire_central_clk_div0_analogrefclkpulse;
	wire  wire_central_clk_div0_coreclkout;
	wire  wire_central_clk_div0_rateswitchdone;
	wire  wire_central_clk_div0_refclkout;
	wire  [1:0]   wire_cent_unit0_clkdivpowerdn;
	wire  [1:0]   wire_cent_unit0_pllpowerdn;
	wire  [1:0]   wire_cent_unit0_pllresetout;
	wire  wire_cent_unit0_quadresetout;
	wire  [5:0]   wire_cent_unit0_txanalogresetout;
	wire  [3:0]   wire_cent_unit0_txctrlout;
	wire  [31:0]   wire_cent_unit0_txdataout;
	wire  [5:0]   wire_cent_unit0_txdetectrxpowerdown;
	wire  [3:0]   wire_cent_unit0_txdigitalresetout;
	wire  [5:0]   wire_cent_unit0_txobpowerdown;
	wire  wire_cent_unit0_txphfifox4byteselout;
	wire  wire_cent_unit0_txphfifox4rdclkout;
	wire  wire_cent_unit0_txphfifox4rdenableout;
	wire  wire_cent_unit0_txphfifox4wrenableout;
	wire  [3:0]   wire_tx_pll0_clk;
	wire  wire_tx_pll0_locked;
	wire  wire_transmit_pcs0_clkout;
	wire  wire_transmit_pcs0_coreclkout;
	wire  [19:0]   wire_transmit_pcs0_dataout;
	wire  wire_transmit_pcs0_forceelecidleout;
	wire  wire_transmit_pcs0_phfiforddisableout;
	wire  wire_transmit_pcs0_phfiforesetout;
	wire  wire_transmit_pcs0_phfifowrenableout;
	wire  wire_transmit_pcs0_txdetectrx;
	wire  wire_transmit_pcs1_clkout;
	wire  wire_transmit_pcs1_coreclkout;
	wire  [19:0]   wire_transmit_pcs1_dataout;
	wire  wire_transmit_pcs1_forceelecidleout;
	wire  wire_transmit_pcs1_phfiforddisableout;
	wire  wire_transmit_pcs1_phfiforesetout;
	wire  wire_transmit_pcs1_phfifowrenableout;
	wire  wire_transmit_pcs1_txdetectrx;
	wire  wire_transmit_pma0_clockout;
	wire  wire_transmit_pma0_dataout;
	wire  wire_transmit_pma1_clockout;
	wire  wire_transmit_pma1_dataout;
	wire cal_blk_powerdown;
	wire  [0:0]  cent_unit_clkdivpowerdn;
	wire  [1:0]  cent_unit_pllpowerdn;
	wire  [1:0]  cent_unit_pllresetout;
	wire  [0:0]  cent_unit_quadresetout;
	wire  [31:0]  cent_unit_tx_xgmdataout;
	wire  [3:0]  cent_unit_txctrlout;
	wire  [5:0]  cent_unit_txdetectrxpowerdn;
	wire  [5:0]  cent_unit_txobpowerdn;
	wire  [3:0]  clk_div_clk0in;
	wire  [1:0]  cmu_analogfastrefclkout;
	wire  [1:0]  cmu_analogrefclkout;
	wire  [0:0]  cmu_analogrefclkpulse;
	wire  [0:0]  coreclkout_wire;
	wire [0:0]  gxb_powerdown;
	wire  [0:0]  int_hiprateswtichdone;
	wire  [1:0]  int_tx_coreclkout;
	wire  [0:0]  int_tx_digitalreset_reg;
	wire  [1:0]  int_tx_phfiforddisableout;
	wire  [1:0]  int_tx_phfiforesetout;
	wire  [1:0]  int_tx_phfifowrenableout;
	wire  [5:0]  int_tx_phfifoxnbytesel;
	wire  [5:0]  int_tx_phfifoxnrdclk;
	wire  [5:0]  int_tx_phfifoxnrdenable;
	wire  [5:0]  int_tx_phfifoxnwrenable;
	wire  [0:0]  int_txcoreclk;
	wire  [0:0]  int_txphfiforddisable;
	wire  [0:0]  int_txphfiforeset;
	wire  [0:0]  int_txphfifowrenable;
	wire  [0:0]  int_txphfifox4byteselout;
	wire  [0:0]  int_txphfifox4rdclkout;
	wire  [0:0]  int_txphfifox4rdenableout;
	wire  [0:0]  int_txphfifox4wrenableout;
	wire  [0:0]  nonusertocmu_out;
	wire  [9:0]  pll0_clkin;
	wire  [3:0]  pll0_out;
	wire  [0:0]  pll_inclk_wire;
	wire  [0:0]  pll_locked_out;
	wire [0:0]  pll_powerdown;
	wire  [1:0]  pllpowerdn_in;
	wire  [1:0]  pllreset_in;
	wire reconfig_clk;
	wire  [0:0]  refclk_pma;
	wire  [5:0]  rx_analogreset_in;
	wire  [3:0]  rx_digitalreset_in;
	wire  [5:0]  tx_analogreset_out;
	wire  [1:0]  tx_clkout_int_wire;
	wire  [1:0]  tx_core_clkout_wire;
	wire  [1:0]  tx_coreclk_in;
	wire  [31:0]  tx_datain_wire;
	wire  [39:0]  tx_dataout_pcs_to_pma;
	wire  [3:0]  tx_digitalreset_in;
	wire  [3:0]  tx_digitalreset_out;
	wire  [1199:0]  tx_dprioin_wire;
	wire  [3:0]  tx_forcedisp_wire;
	wire [1:0]  tx_invpolarity;
	wire  [1:0]  tx_localrefclk;
	wire [1:0]  tx_phfiforeset;
	wire  [1799:0]  tx_pmadprioin_wire;
	wire  [1:0]  txdetectrxout;

	// synopsys translate_off
	initial
		tx_digitalreset_reg0c[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
		  tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
	// synopsys translate_off
	initial
		tx_digitalreset_reg0c[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
		  tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
	// synopsys translate_off
	initial
		tx_digitalreset_reg0c[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
		  tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
	assign
		wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
	assign
		wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
	arriaii_hssi_calibration_block   cal_blk0
	( 
	.calibrationstatus(),
	.clk(cal_blk_clk),
	.enabletestbus(1'b1),
	.nonusertocmu(wire_cal_blk0_nonusertocmu),
	.powerdn(cal_blk_powerdown)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.testctrl(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	arriaii_hssi_clock_divider   central_clk_div0
	( 
	.analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
	.analogfastrefclkoutshifted(),
	.analogrefclkout(wire_central_clk_div0_analogrefclkout),
	.analogrefclkoutshifted(),
	.analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
	.analogrefclkpulseshifted(),
	.clk0in(clk_div_clk0in[3:0]),
	.coreclkout(wire_central_clk_div0_coreclkout),
	.dpriodisable(1'b1),
	.dprioout(),
	.powerdn(cent_unit_clkdivpowerdn[0]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchbaseclock(),
	.rateswitchdone(wire_central_clk_div0_rateswitchdone),
	.rateswitchout(),
	.refclkout(wire_central_clk_div0_refclkout)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.clk1in({4{1'b0}}),
	.dprioin({100{1'b0}}),
	.rateswitch(1'b0),
	.rateswitchbaseclkin({2{1'b0}}),
	.rateswitchdonein({2{1'b0}}),
	.refclkdig(1'b0),
	.refclkin({2{1'b0}}),
	.vcobypassin(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		central_clk_div0.divide_by = 5,
		central_clk_div0.divider_type = "CENTRAL_ENHANCED",
		central_clk_div0.effective_data_rate = "3125 Mbps",
		central_clk_div0.enable_dynamic_divider = "false",
		central_clk_div0.enable_refclk_out = "true",
		central_clk_div0.inclk_select = 0,
		central_clk_div0.logical_channel_address = 0,
		central_clk_div0.pre_divide_by = 1,
		central_clk_div0.refclkin_select = 0,
		central_clk_div0.select_local_refclk = "true",
		central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
		central_clk_div0.sim_analogrefclkout_phase_shift = 0,
		central_clk_div0.sim_coreclkout_phase_shift = 0,
		central_clk_div0.sim_refclkout_phase_shift = 0,
		central_clk_div0.use_coreclk_out_post_divider = "true",
		central_clk_div0.use_refclk_post_divider = "false",
		central_clk_div0.use_vco_bypass = "false",
		central_clk_div0.lpm_type = "arriaii_hssi_clock_divider";
	arriaii_hssi_cmu   cent_unit0
	( 
	.adet({4{1'b0}}),
	.alignstatus(),
	.autospdx4configsel(),
	.autospdx4rateswitchout(),
	.autospdx4spdchg(),
	.clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
	.cmudividerdprioout(),
	.cmuplldprioout(),
	.digitaltestout(),
	.dpclk(reconfig_clk),
	.dpriodisable(1'b1),
	.dpriodisableout(),
	.dprioin(1'b0),
	.dprioload(1'b0),
	.dpriooe(),
	.dprioout(),
	.enabledeskew(),
	.extra10gout(),
	.fiforesetrd(),
	.lccmutestbus(),
	.nonuserfromcal(nonusertocmu_out[0]),
	.phfifiox4ptrsreset(),
	.pllpowerdn(wire_cent_unit0_pllpowerdn),
	.pllresetout(wire_cent_unit0_pllresetout),
	.quadreset(gxb_powerdown[0]),
	.quadresetout(wire_cent_unit0_quadresetout),
	.rateswitchdonein(int_hiprateswtichdone[0]),
	.rdalign({4{1'b0}}),
	.rdenablesync(1'b0),
	.recovclk(1'b0),
	.refclkdividerdprioin({2{1'b0}}),
	.refclkdividerdprioout(),
	.rxadcepowerdown(),
	.rxadceresetout(),
	.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
	.rxanalogresetout(),
	.rxcrupowerdown(),
	.rxcruresetout(),
	.rxctrl({4{1'b0}}),
	.rxctrlout(),
	.rxdatain({32{1'b0}}),
	.rxdataout(),
	.rxdatavalid({4{1'b0}}),
	.rxdigitalreset({rx_digitalreset_in[3:0]}),
	.rxdigitalresetout(),
	.rxibpowerdown(),
	.rxpcsdprioout(),
	.rxphfifox4byteselout(),
	.rxphfifox4rdenableout(),
	.rxphfifox4wrclkout(),
	.rxphfifox4wrenableout(),
	.rxpmadprioout(),
	.rxrunningdisp({4{1'b0}}),
	.scanout(),
	.syncstatus({4{1'b0}}),
	.testout(),
	.txanalogresetout(wire_cent_unit0_txanalogresetout),
	.txclk(refclk_pma[0]),
	.txcoreclk(int_txcoreclk[0]),
	.txctrl({4{1'b0}}),
	.txctrlout(wire_cent_unit0_txctrlout),
	.txdatain({32{1'b0}}),
	.txdataout(wire_cent_unit0_txdataout),
	.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
	.txdigitalreset({tx_digitalreset_in[3:0]}),
	.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
	.txdividerpowerdown(),
	.txobpowerdown(wire_cent_unit0_txobpowerdown),
	.txpcsdprioout(),
	.txphfiforddisable(int_txphfiforddisable[0]),
	.txphfiforeset(int_txphfiforeset[0]),
	.txphfifowrenable(int_txphfifowrenable[0]),
	.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
	.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
	.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
	.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
	.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
	.txpmadprioout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.cmudividerdprioin({600{1'b0}}),
	.cmuplldprioin({1800{1'b0}}),
	.extra10gin({7{1'b0}}),
	.fixedclk({6{1'b0}}),
	.lccmurtestbussel({3{1'b0}}),
	.pmacramtest(1'b0),
	.rateswitch(1'b0),
	.rxclk(1'b0),
	.rxcoreclk(1'b0),
	.rxpcsdprioin({1600{1'b0}}),
	.rxphfifordenable(1'b1),
	.rxphfiforeset(1'b0),
	.rxphfifowrdisable(1'b0),
	.rxpmadprioin({1800{1'b0}}),
	.rxpowerdown({6{1'b0}}),
	.scanclk(1'b0),
	.scanin({23{1'b0}}),
	.scanmode(1'b0),
	.scanshift(1'b0),
	.testin({10000{1'b0}}),
	.txpcsdprioin({600{1'b0}}),
	.txpmadprioin({1800{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
		cent_unit0.auto_spd_phystatus_notify_count = 14,
		cent_unit0.bonded_quad_mode = "none",
		cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
		cent_unit0.in_xaui_mode = "false",
		cent_unit0.offset_all_errors_align = "false",
		cent_unit0.pipe_auto_speed_nego_enable = "false",
		cent_unit0.pipe_freq_scale_mode = "Frequency",
		cent_unit0.pma_done_count = 249950,
		cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
		cent_unit0.rx0_auto_spd_self_switch_enable = "false",
		cent_unit0.rx0_ph_fifo_reg_mode = "false",
		cent_unit0.tx0_auto_spd_self_switch_enable = "false",
		cent_unit0.tx0_channel_bonding = "x4",
		cent_unit0.tx0_ph_fifo_reg_mode = "false",
		cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
		cent_unit0.tx0_use_double_data_mode = "true",
		cent_unit0.tx0_wr_clk_mux_select = "core_clk",
		cent_unit0.use_deskew_fifo = "false",
		cent_unit0.vcceh_voltage = "Auto",
		cent_unit0.lpm_type = "arriaii_hssi_cmu";
	arriaii_hssi_pll   tx_pll0
	( 
	.areset(pllreset_in[0]),
	.clk(wire_tx_pll0_clk),
	.dataout(),
	.dpriodisable(1'b1),
	.dprioout(),
	.freqlocked(),
	.inclk({pll0_clkin[9:0]}),
	.locked(wire_tx_pll0_locked),
	.pfdfbclkout(),
	.pfdrefclkout(),
	.powerdown(pllpowerdn_in[0]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datain(1'b0),
	.dprioin({300{1'b0}}),
	.earlyeios(1'b0),
	.extra10gin({6{1'b0}}),
	.locktorefclk(1'b1),
	.pfdfbclk(1'b0),
	.rateswitch(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		tx_pll0.bandwidth_type = "Auto",
		tx_pll0.channel_num = 4,
		tx_pll0.dprio_config_mode = 6'h00,
		tx_pll0.inclk0_input_period = 6400,
		tx_pll0.input_clock_frequency = "156.25 MHz",
		tx_pll0.logical_tx_pll_number = 0,
		tx_pll0.m = 10,
		tx_pll0.n = 1,
		tx_pll0.pfd_clk_select = 0,
		tx_pll0.pfd_fb_select = "internal",
		tx_pll0.pll_type = "CMU",
		tx_pll0.use_refclk_pin = "false",
		tx_pll0.vco_post_scale = 1,
		tx_pll0.lpm_type = "arriaii_hssi_pll";
	arriaii_hssi_tx_pcs   transmit_pcs0
	( 
	.clkout(wire_transmit_pcs0_clkout),
	.coreclk(tx_coreclk_in[0]),
	.coreclkout(wire_transmit_pcs0_coreclkout),
	.ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
	.datain({{24{1'b0}}, tx_datain_wire[15:0]}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs0_dataout),
	.detectrxloop(1'b0),
	.digitalreset(tx_digitalreset_out[0]),
	.dpriodisable(1'b1),
	.dprioin(tx_dprioin_wire[149:0]),
	.dprioout(),
	.enrevparallellpbk(1'b0),
	.forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
	.grayelecidleinferselout(),
	.hiptxclkout(),
	.invpol(tx_invpolarity[0]),
	.iqpphfifobyteselout(),
	.iqpphfifordclkout(),
	.iqpphfifordenableout(),
	.iqpphfifowrenableout(),
	.localrefclk(tx_localrefclk[0]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifooverflow(),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[0]),
	.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
	.pipeenrevparallellpbkout(),
	.pipepowerdownout(),
	.pipepowerstateout(),
	.pipestatetransdone(1'b0),
	.powerdn({2{1'b0}}),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[0]),
	.revparallelfdbk({20{1'b0}}),
	.txdetectrx(wire_transmit_pcs0_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[0]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.dispval({4{1'b0}}),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.hipdatain({10{1'b0}}),
	.hipdetectrxloop(1'b0),
	.hipelecidleinfersel({3{1'b0}}),
	.hipforceelecidle(1'b0),
	.hippowerdn({2{1'b0}}),
	.hiptxdeemph(1'b0),
	.hiptxmargin({3{1'b0}}),
	.iqpphfifoxnbytesel({2{1'b0}}),
	.iqpphfifoxnrdclk({2{1'b0}}),
	.iqpphfifoxnrdenable({2{1'b0}}),
	.iqpphfifoxnwrenable({2{1'b0}}),
	.phfifobyteserdisable(1'b0),
	.phfifoptrsreset(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxnptrsreset({3{1'b0}}),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.pipetxswing(1'b0),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs0.allow_polarity_inversion = "false",
		transmit_pcs0.auto_spd_self_switch_enable = "false",
		transmit_pcs0.bitslip_enable = "false",
		transmit_pcs0.channel_bonding = "x4",
		transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
		transmit_pcs0.channel_width = 16,
		transmit_pcs0.core_clock_0ppm = "false",
		transmit_pcs0.datapath_low_latency_mode = "false",
		transmit_pcs0.datapath_protocol = "basic",
		transmit_pcs0.disable_ph_low_latency_mode = "false",
		transmit_pcs0.disparity_mode = "none",
		transmit_pcs0.dprio_config_mode = 6'h00,
		transmit_pcs0.elec_idle_delay = 6,
		transmit_pcs0.enable_bit_reversal = "false",
		transmit_pcs0.enable_idle_selection = "false",
		transmit_pcs0.enable_reverse_parallel_loopback = "false",
		transmit_pcs0.enable_self_test_mode = "false",
		transmit_pcs0.enable_symbol_swap = "false",
		transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs0.enc_8b_10b_mode = "normal",
		transmit_pcs0.force_echar = "false",
		transmit_pcs0.force_kchar = "false",
		transmit_pcs0.hip_enable = "false",
		transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
		transmit_pcs0.ph_fifo_reg_mode = "false",
		transmit_pcs0.ph_fifo_xn_mapping0 = "none",
		transmit_pcs0.ph_fifo_xn_mapping1 = "none",
		transmit_pcs0.ph_fifo_xn_mapping2 = "central",
		transmit_pcs0.ph_fifo_xn_select = 2,
		transmit_pcs0.pipe_auto_speed_nego_enable = "false",
		transmit_pcs0.pipe_freq_scale_mode = "Frequency",
		transmit_pcs0.prbs_cid_pattern = "false",
		transmit_pcs0.protocol_hint = "basic",
		transmit_pcs0.refclk_select = "cmu_clock_divider",
		transmit_pcs0.self_test_mode = "incremental",
		transmit_pcs0.use_double_data_mode = "true",
		transmit_pcs0.use_serializer_double_data_mode = "false",
		transmit_pcs0.wr_clk_mux_select = "core_clk",
		transmit_pcs0.lpm_type = "arriaii_hssi_tx_pcs";
	arriaii_hssi_tx_pcs   transmit_pcs1
	( 
	.clkout(wire_transmit_pcs1_clkout),
	.coreclk(tx_coreclk_in[1]),
	.coreclkout(wire_transmit_pcs1_coreclkout),
	.ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
	.datain({{24{1'b0}}, tx_datain_wire[31:16]}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs1_dataout),
	.detectrxloop(1'b0),
	.digitalreset(tx_digitalreset_out[1]),
	.dpriodisable(1'b1),
	.dprioin(tx_dprioin_wire[299:150]),
	.dprioout(),
	.enrevparallellpbk(1'b0),
	.forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs1_forceelecidleout),
	.grayelecidleinferselout(),
	.hiptxclkout(),
	.invpol(tx_invpolarity[1]),
	.iqpphfifobyteselout(),
	.iqpphfifordclkout(),
	.iqpphfifordenableout(),
	.iqpphfifowrenableout(),
	.localrefclk(tx_localrefclk[1]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifooverflow(),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[1]),
	.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
	.pipeenrevparallellpbkout(),
	.pipepowerdownout(),
	.pipepowerstateout(),
	.pipestatetransdone(1'b0),
	.powerdn({2{1'b0}}),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[0]),
	.revparallelfdbk({20{1'b0}}),
	.txdetectrx(wire_transmit_pcs1_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[1]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[15:8]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.dispval({4{1'b0}}),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.hipdatain({10{1'b0}}),
	.hipdetectrxloop(1'b0),
	.hipelecidleinfersel({3{1'b0}}),
	.hipforceelecidle(1'b0),
	.hippowerdn({2{1'b0}}),
	.hiptxdeemph(1'b0),
	.hiptxmargin({3{1'b0}}),
	.iqpphfifoxnbytesel({2{1'b0}}),
	.iqpphfifoxnrdclk({2{1'b0}}),
	.iqpphfifoxnrdenable({2{1'b0}}),
	.iqpphfifoxnwrenable({2{1'b0}}),
	.phfifobyteserdisable(1'b0),
	.phfifoptrsreset(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxnptrsreset({3{1'b0}}),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.pipetxswing(1'b0),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs1.allow_polarity_inversion = "false",
		transmit_pcs1.auto_spd_self_switch_enable = "false",
		transmit_pcs1.bitslip_enable = "false",
		transmit_pcs1.channel_bonding = "x4",
		transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
		transmit_pcs1.channel_width = 16,
		transmit_pcs1.core_clock_0ppm = "false",
		transmit_pcs1.datapath_low_latency_mode = "false",
		transmit_pcs1.datapath_protocol = "basic",
		transmit_pcs1.disable_ph_low_latency_mode = "false",
		transmit_pcs1.disparity_mode = "none",
		transmit_pcs1.dprio_config_mode = 6'h00,
		transmit_pcs1.elec_idle_delay = 6,
		transmit_pcs1.enable_bit_reversal = "false",
		transmit_pcs1.enable_idle_selection = "false",
		transmit_pcs1.enable_reverse_parallel_loopback = "false",
		transmit_pcs1.enable_self_test_mode = "false",
		transmit_pcs1.enable_symbol_swap = "false",
		transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs1.enc_8b_10b_mode = "normal",
		transmit_pcs1.force_echar = "false",
		transmit_pcs1.force_kchar = "false",
		transmit_pcs1.hip_enable = "false",
		transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
		transmit_pcs1.ph_fifo_reg_mode = "false",
		transmit_pcs1.ph_fifo_xn_mapping0 = "none",
		transmit_pcs1.ph_fifo_xn_mapping1 = "none",
		transmit_pcs1.ph_fifo_xn_mapping2 = "central",
		transmit_pcs1.ph_fifo_xn_select = 2,
		transmit_pcs1.pipe_auto_speed_nego_enable = "false",
		transmit_pcs1.pipe_freq_scale_mode = "Frequency",
		transmit_pcs1.prbs_cid_pattern = "false",
		transmit_pcs1.protocol_hint = "basic",
		transmit_pcs1.refclk_select = "cmu_clock_divider",
		transmit_pcs1.self_test_mode = "incremental",
		transmit_pcs1.use_double_data_mode = "true",
		transmit_pcs1.use_serializer_double_data_mode = "false",
		transmit_pcs1.wr_clk_mux_select = "core_clk",
		transmit_pcs1.lpm_type = "arriaii_hssi_tx_pcs";
	arriaii_hssi_tx_pma   transmit_pma0
	( 
	.clockout(wire_transmit_pma0_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
	.dataout(wire_transmit_pma0_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
	.dftout(),
	.dpriodisable(1'b1),
	.dprioin(tx_pmadprioin_wire[299:0]),
	.dprioout(),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk2in({2{1'b0}}),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(1'b0),
	.powerdn(cent_unit_txobpowerdn[0]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in(cmu_analogrefclkout[1:0]),
	.refclk1inpulse(cmu_analogrefclkpulse[0]),
	.refclk2in({2{1'b0}}),
	.refclk2inpulse(1'b0),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[0]),
	.rxdetectvalidout(),
	.rxfoundout(),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[0])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma0.analog_power = "1.5V",
		transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
		transmit_pma0.channel_type = "auto",
		transmit_pma0.clkin_select = 1,
		transmit_pma0.clkmux_delay = "false",
		transmit_pma0.common_mode = "0.65V",
		transmit_pma0.dprio_config_mode = 6'h00,
		transmit_pma0.enable_reverse_serial_loopback = "false",
		transmit_pma0.logical_channel_address = (starting_channel_number + 0),
		transmit_pma0.logical_protocol_hint_0 = "basic",
		transmit_pma0.low_speed_test_select = 0,
		transmit_pma0.physical_clkin1_mapping = "x4",
		transmit_pma0.preemp_pretap = 0,
		transmit_pma0.preemp_pretap_inv = "false",
		transmit_pma0.preemp_tap_1 = 0,
		transmit_pma0.preemp_tap_2 = 0,
		transmit_pma0.preemp_tap_2_inv = "false",
		transmit_pma0.protocol_hint = "basic",
		transmit_pma0.rx_detect = 0,
		transmit_pma0.serialization_factor = 10,
		transmit_pma0.slew_rate = "off",
		transmit_pma0.termination = "OCT 100 Ohms",
		transmit_pma0.use_external_termination = "false",
		transmit_pma0.use_pma_direct = "false",
		transmit_pma0.use_ser_double_data_mode = "false",
		transmit_pma0.vod_selection = 4,
		transmit_pma0.lpm_type = "arriaii_hssi_tx_pma";
	arriaii_hssi_tx_pma   transmit_pma1
	( 
	.clockout(wire_transmit_pma1_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
	.dataout(wire_transmit_pma1_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
	.dftout(),
	.dpriodisable(1'b1),
	.dprioin(tx_pmadprioin_wire[599:300]),
	.dprioout(),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk2in({2{1'b0}}),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(1'b0),
	.powerdn(cent_unit_txobpowerdn[1]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in(cmu_analogrefclkout[1:0]),
	.refclk1inpulse(cmu_analogrefclkpulse[0]),
	.refclk2in({2{1'b0}}),
	.refclk2inpulse(1'b0),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[1]),
	.rxdetectvalidout(),
	.rxfoundout(),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[1])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma1.analog_power = "1.5V",
		transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
		transmit_pma1.channel_type = "auto",
		transmit_pma1.clkin_select = 1,
		transmit_pma1.clkmux_delay = "false",
		transmit_pma1.common_mode = "0.65V",
		transmit_pma1.dprio_config_mode = 6'h00,
		transmit_pma1.enable_reverse_serial_loopback = "false",
		transmit_pma1.logical_channel_address = (starting_channel_number + 1),
		transmit_pma1.logical_protocol_hint_0 = "basic",
		transmit_pma1.low_speed_test_select = 0,
		transmit_pma1.physical_clkin1_mapping = "x4",
		transmit_pma1.preemp_pretap = 0,
		transmit_pma1.preemp_pretap_inv = "false",
		transmit_pma1.preemp_tap_1 = 0,
		transmit_pma1.preemp_tap_2 = 0,
		transmit_pma1.preemp_tap_2_inv = "false",
		transmit_pma1.protocol_hint = "basic",
		transmit_pma1.rx_detect = 0,
		transmit_pma1.serialization_factor = 10,
		transmit_pma1.slew_rate = "off",
		transmit_pma1.termination = "OCT 100 Ohms",
		transmit_pma1.use_external_termination = "false",
		transmit_pma1.use_pma_direct = "false",
		transmit_pma1.use_ser_double_data_mode = "false",
		transmit_pma1.vod_selection = 4,
		transmit_pma1.lpm_type = "arriaii_hssi_tx_pma";
	assign
		cal_blk_powerdown = 1'b0,
		cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
		cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
		cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
		cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
		cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
		cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
		cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
		cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
		clk_div_clk0in = {pll0_out[3:0]},
		cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
		cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
		cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
		coreclkout = {coreclkout_wire[0]},
		coreclkout_wire = {wire_central_clk_div0_coreclkout},
		gxb_powerdown = 1'b0,
		int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
		int_tx_coreclkout = {wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
		int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
		int_tx_phfiforddisableout = {wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
		int_tx_phfiforesetout = {wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
		int_tx_phfifowrenableout = {wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
		int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
		int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
		int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
		int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
		int_txcoreclk = {int_tx_coreclkout[0]},
		int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
		int_txphfiforeset = {int_tx_phfiforesetout[0]},
		int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
		int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
		int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
		int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
		int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
		nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
		pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
		pll0_out = {wire_tx_pll0_clk[3:0]},
		pll_inclk_wire = {pll_inclk},
		pll_locked = {pll_locked_out[0]},
		pll_locked_out = {wire_tx_pll0_locked},
		pll_powerdown = 1'b0,
		pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
		pllreset_in = {1'b0, cent_unit_pllresetout[0]},
		reconfig_clk = 1'b0,
		refclk_pma = {wire_central_clk_div0_refclkout},
		tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
		tx_clkout = {tx_core_clkout_wire[1:0]},
		tx_clkout_int_wire = {wire_transmit_pcs1_clkout, wire_transmit_pcs0_clkout},
		tx_core_clkout_wire = {2{tx_clkout_int_wire[0]}},
		tx_coreclk_in = {2{coreclkout_wire[0]}},
		tx_datain_wire = {tx_datain[31:0]},
		tx_dataout = {wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
		tx_dataout_pcs_to_pma = {wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
		tx_digitalreset_in = {{2{1'b0}}, {2{int_tx_digitalreset_reg[0]}}},
		tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
		tx_dprioin_wire = {{900{1'b0}}, {2{{150{1'b0}}}}},
		tx_forcedisp_wire = {2{{2{1'b0}}}},
		tx_invpolarity = {2{1'b0}},
		tx_localrefclk = {wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
		tx_phfiforeset = {2{1'b0}},
		tx_pmadprioin_wire = {{1200{1'b0}}, {2{{300{1'b0}}}}},
		txdetectrxout = {wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx};
endmodule //trans_alt4gxb
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module trans (
	cal_blk_clk,
	pll_inclk,
	tx_ctrlenable,
	tx_datain,
	tx_digitalreset,
	coreclkout,
	pll_locked,
	tx_clkout,
	tx_dataout);

	input	  cal_blk_clk;
	input	  pll_inclk;
	input	[3:0]  tx_ctrlenable;
	input	[31:0]  tx_datain;
	input	[0:0]  tx_digitalreset;
	output	[0:0]  coreclkout;
	output	[0:0]  pll_locked;
	output	[1:0]  tx_clkout;
	output	[1:0]  tx_dataout;

	wire [0:0] sub_wire0;
	wire [0:0] sub_wire1;
	wire [1:0] sub_wire2;
	wire [1:0] sub_wire3;
	wire [0:0] coreclkout = sub_wire0[0:0];
	wire [0:0] pll_locked = sub_wire1[0:0];
	wire [1:0] tx_clkout = sub_wire2[1:0];
	wire [1:0] tx_dataout = sub_wire3[1:0];

	trans_alt4gxb	trans_alt4gxb_component (
				.pll_inclk (pll_inclk),
				.tx_datain (tx_datain),
				.tx_digitalreset (tx_digitalreset),
				.cal_blk_clk (cal_blk_clk),
				.tx_ctrlenable (tx_ctrlenable),
				.coreclkout (sub_wire0),
				.pll_locked (sub_wire1),
				.tx_clkout (sub_wire2),
				.tx_dataout (sub_wire3));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "3125.0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "3125"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "62.5"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "156.25"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 78.125 97.65625 125.0 156.25 195.3125 250.0 312.5 390.625 500.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "3125"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "156.25"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "X4"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "3125 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "156.25 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "2"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "tx"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "2"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATAPATH_LOW_LATENCY_MODE STRING "false"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "3125"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_FLIP_TX_IN STRING "false"
// Retrieval info: CONSTANT: TX_FORCE_DISPARITY_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "6400"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "10"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 2 0 OUTPUT NODEFVAL "tx_clkout[1..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 4 0 INPUT NODEFVAL "tx_ctrlenable[3..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 32 0 INPUT NODEFVAL "tx_datain[31..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 2 0 OUTPUT NODEFVAL "tx_dataout[1..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 4 0 tx_ctrlenable 0 0 4 0
// Retrieval info: CONNECT: @tx_datain 0 0 32 0 tx_datain 0 0 32 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 2 0 @tx_clkout 0 0 2 0
// Retrieval info: CONNECT: tx_dataout 0 0 2 0 @tx_dataout 0 0 2 0
// Retrieval info: GEN_FILE: TYPE_NORMAL trans.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL trans.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL trans.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL trans.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL trans.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL trans_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL trans_bb.v TRUE
// Retrieval info: LIB_FILE: arriaii_hssi
// Retrieval info: CBX_MODULE_PREFIX: ON
