DSP Input Data Buffers
Last Update: 13-Dec-99
Event Data in both DSPs 1-4 and DSP 5 is storedin separate Data
Buffers for each possible input data source.
A finished event's worth of data in the DSP's FIFO is flagged by the
presence of an input word on the DSP's serial
input port (MCBSP1) which will cause an interrupt to the DSP.
DSP 5 requires these separate buffers to deal with event
interleaving of data from DSPs 1-4 and possible full-readout data.
Separate buffers for each input are not stictly necessary for DSPs 1-4
since data arrives ordered by source and event.
They are used for to be more consistent with DSP 5.
The main requirement of the buffer management scheme is speed.
This has several consequences.
- A request for data input to the DSP always takes precedence over
any other process running in the DSP. This implies that we will
use serial port interrupts (at some point).
- No error checking is performed as the data is read into
buffers. The physics algorithm will be responsible for data
verification.
Each buffer will be circular and will be allowed to contain variable size
entries.
This requires a slightly more complicated algorithm for managing
read and write pointers than for the case of fixed element size,
however, savings in memory and speed using this method should be
substantial.
In particular, variable size entries mean that an overflow
memory must be included at the end of each buffer's main
memory to allow events to always be transferred to the buffer in
single blocks by DMA.
Each buffer thus has two components:
- Main Memory: the main part of the buffer. It's size should be
determined by the average event size for the associated input
channel's data times the number of buffer elements required
(16?)
- Overflow Memory: used to absorb input events that would overflow
the Main Memory. This allows us to wrap around the buffer in a
controlled way. It must be larger than the maximum size of an
event on that input.
Writes to the Buffer will be performed by a DMA of the number of words
specified in the DSP FPGA Stack Word
from the DSP FIFO to a starting buffer location contained in a write
pointer kept by the Buffer Manager.
Care must be taken that the data waiting to be written will not
overfill the buffer.
If this is the case, the buffer manager will return a buff_full
condition and return to the main algorithm until memory is released
from the buffers by reading an event.
The buffers are read by the main algorithm running in the DSP which
puts the event data to a temporary storage area.
This temporary storage area is accessed by the physics
algorithm running in the DSP which then doesn't need to know
anything about the buffer structure.
Because the physics algorithm may not always keep up with the rate of
data input, pointers to full buffer elements must be maintained in a
read pointer stack which is read as a FIFO.
DSP 1-4 Data Buffers
Since the SLIC has 16 total inputs there can be at most 16
buffers in any DSP.