Updated: 15-Aug-2001

There are three basic initialization modes in the SLICs.

1. Cold Start: Performed when the SLICs are powered up.
2. Warm Start: A complete reinitialization of all elements of the SLICs.
3. SCL Init: A quick restart (clears inputs, outputs and buffers) at the request of the Trigger Framework. Note that here we have to consider the cases of:
   • responding to SCL init
   • requesting SCL init.

Each of these modes are described in more detail below.

The following is performed when the SLICs are powered on.

Operation	Comments
Load FPGAs from PROM	VME FPGA Output buffer FPGA Output hotlink FPGA DSP FPGAs (1-5)
Warm Start	see below

The purpose of the warm start is to completely reinitialize the SLICs. Everything is reset, the DSPs are rebooted and all downloads are redone. Preliminary tests indicate that the time it takes to do this should be completely dominated by reloading the Look Up Tables into the DSP SBRAM. The next most costly operations are loading code to the Input and Link FPGAs - which take 100's of ms.

Note that the warmstart is not terribly effected by the order of the operations given in the table below.

	Operation (function)	Comments
Warmstart in the Driver
1.	Read SLIC Params RCP (*)	Fill slicpars and dspars structs Active Inputs Input Channel Director Bits DSP Output Director Bits etc, etc, etc... Should use identical RCP to simulation Can also set up in Test Mode using appropriate RCP file
2.	Load Input/Link FPGA Code (altera_config_input/link)	Reset Input/Link FPGAs All FPGAs loaded with same code
3.	Reset/Resynch Hotlinks (resethotlink)
4.	Disable Token (resettokenring)
5.	Setup Output Channel (outchansetup)	Reset FPGAs (outchanreset) - resets output hotlink fpga - zero's counters Clear Output FIFO (*) Set to DAQ mode (outchansetmode) Set Big Endian (outchansetendian) Set no BIST (outchansetbist)
6.	Setup Input Channels (inpchansetup)	Reset FPGAs (inpchanreset) - zero's counters Clear Input FIFO (*) Set to DAQ mode (inpchansetmode) Set Big Endian (inpchansetendian) Set Last Chip (inpchansetlast) Set no BIST (inpchansetbist)
7.	Setup Link (lnkchansetup)	Reset FPGAs (lnkchanreset) - zero's counters Select or Pass Mode (lnkchansetpass) Set Last Chip (lnkchansetlast) Set Director Bits (lnkchansetdirectors)
8.	Reset DSPs (dsp_hardreset)	Is this necessary???
9.	Reset DSP+Peripherals (dsp_bootresets)	Reset FIFO Reset DSP FPGA Reset Serial Port Reset Link Set flagout=0 (groundstate) Hold Off boot (holdboot)
10.	Boot DSP (dsp_boot)	Load boot exe to FIFO (loadfile boot.hex) - release holdboot Wait for DSP to read file and execute - handshaking DSP - Driver Reset DSP fifo Load boot-dat to fifo (loadfile data.hex) Wait for DSP to read file and execute rest of boot Boot Verify Tests (dspbootverify) - Toggle flagout/flagin (test_togl) - Test Serial input/output (test_ser) - Read all DSP registers (readdspregs)
11.	Setup DSP FPGA (dsp_setup)	Reset Peripherals (dsp_softreset) Set output dirbits Set DSP ID Set rest of Control par's to defaults (*) Reset DSP FIFO (dspfiforeset) Set output to VME (dspcomoutmode) - necessary for later handshaking
12.	Init DSP Input Buffers (*)	Command to DSPs Wait for Acknowledge
13.	Init Monitoring Mem (DSP 5) (*)	Command to DSP 5 Wait for Acknowledge
14.	Look Up Tables to SBRAM (dspcommand7)	LUT Data to FIFO Read FIFO to SBRAM command to DSP Wait for Acknowledge
15.	Start Algorithms (*)	Command to DSPs Wait for Acknowledge
Boot Sequence in DSPs
1.	Low Level Boot (boot_ker.sa)	Executed at start of bootup before initialized data is loaded init EMIF init MCBSP0 init SRGR hadshake with driver Load Initialized data sections handshake with driver Jump to c-code entry point
2.	Init Peripherals (boot.c)	EMIF (emif_init) MCBSP 0 (gen purpose i/o) (mcbsp_init) MCBSP 1 (mcbsp_init) - SRGR (set serial read/write to 80 MHz) DMA Channels (dma_init) - Channel 1: 5x8-bit (for output) - Channel 0: 32-bit (for memory/serial reads)
3.	Boot Verification (boot.c)	Toggle flagout/flagin (test_togl) Test Serial input/output (test_ser) Read all DSP registers (readdspregs)
4.	Jump to Command Loop (*)	Wait for next command
Algorithm Initialization in DSPs
	Input Buffer Setup (?)	Memory start, size, active channels... Handshake with Driver
	Monitoring Mem Setup (DSP 5) (*)	Memory start, size Handshake with Driver
	Load LUT to SBRAM (loadmem)	Read source, dest, size DMA data source to dest Handshake with Driver
	Jump to Algo Entry (*)	on command from Driver Handshake with Driver

(*) Code does not exist or must be heavily modified.

As I understand it, the following actions are required when performing an SCL Init. (These must be written down somewhere - but I can't find it.)

• Finish and send out the current event (or send a dummy event).
• Clear all inputs and wait until no data is sent to them.
• Resynch inputs.
• Reset all FIFOs and buffers.
• Clear all outputs.
• Restart algorithms.

We need to avoid the following in our SCL Init function.

• Reloading FPGA code
  This takes a long time and would mean reconfiguring as well.
• Reconfiguring the Inputs/Link
  Would require re-downloading the slic pars RCP file.
• Rebooting the DSPs
  Would have to reload the boot files and reconfig the DSPs
• Reloading the Look Up Tables
  This will take a long time. But it would be good if we could check for any LUT corruption.

The SCL Init process in the SLICs will (probably) be controlled from the driver program running in the Alpha(?) That way the Alpha takes care of all communications with the Trigger Framework.

Commannds must be sent from the driver code to the SLICs in a specific order so that there is no possibility of having an upstream element send data to something downstream after we think that we've cleared the downstream element.

Additionally, we will need to send the SLC Init command to the DSPs via an interrupt - the extint7 line from the DSP FPGA to the DSP. This is the only external interrupt line we have available going into the DSP - so it's a bit of a shame to waste it on SCL Init. However, if we tried to send the SCL Init command via the normal path (the DSP input serial port via the DSP FPGA stack) we risk that the command could be delayed while any other stackwords that are already there are dealt with. In the worst case, the SCL Init command would never reach the DSP if it were hung somewhere out of the command loop.

	Operation (function)	Comments
SCL Init in the Driver
1.	Receive SCL Init (*)	Acknowlege to Alpha register slic_scl_init=1
2.	Disable Token (resettokenring)	Stops data to DSPs 1-4
3.	Reset Inputs Counters/FIFOs (*)	Do not reset FPGAs - retain config Zero EV_COUNT,ERRORS Reset Input FIFOs will check later for more data
3.	Reset Link Counters (*)	Do not reset FPGAs - retain director bits Zero EV_COUNT will restart token later
4.	Resynch Hotlinks (resethotlink)
5.	SCL Init to DSPs 1-4 (*)	Send via extint7 Wait for acknowledge from DSP Stops data to DSP 5 (see below for init sequence in DSPs)
6.	SCL Init to DSP 5 (*)	Send via extint7 Wait for monitoring from DSP Dummy event sent out here Stops data to Output (see below for init sequence in DSPs)
7.	Receive Monitoring Data (*)	Sent by DSP 5
8.	Reset Output Counters/FIFOs (*)	Do not reset FPGAs - retain config Zero EV_COUNT Reset Output FIFOs
9.	Check Inputs for more Data (*)	Could use EV_COUNT and/or IDLE If data - clear and check again Loop until no data
10.	Restart Token (enableautotoken)
11.	SCL Init Done to Alpha (*)	Set register slic_scl_init=0
SCL Init in the DSPs - Interrupt Routine
1.	Receive SCL Init (*)	Jump to interrupt routine Acknowlege to Driver
2.	Reinit Peripherals??? (emif_init, mcbsp_gpio, mcbsp_init, dma_init)	emif serial ports dma Is this necessary???
3.	Send Dummy Event (DSP 5) (*)	Only if there is data in Input buffers Need to find event number somewhere Note: worker DSPs don't send out anything - they just reset.
4.	Memory Checks? (*)	Look Up Table??? Construct error flags for Acknowledge
5.	Monitoring to Driver (DSP 5) (*)	Out mode to VME Send Monitoring Data via serial port Out mode to Link If this is not done, mon data is lost
6.	Clear Monitoring Reg's (DSP 5) (*)
7.	SCL Init Done to Driver (*)	Out mode to VME Send Error Flags via serial port Out mode to Link
8.	Jump to Algorithm Entry (*)	Set Interrupt Return Pointer to algo entry Return from interrupt - takes care of problems with nested interrupts Input Buffer struct cleared at algo start

(*) Code does not exist or must be heavily modified.

DSP-5 will request SCL Init by setting a bit in the trailer that it sends to the Alpha. It is up to the Alpha to interpret this bit and actually pass the init request on to the MBT.

SCL Init will be requested under the following conditions.

1. N events where one or more of the SLIC's data sources have an event number mismatch. (We should probably start off with N=1.
2. Algorithm failure in a worker DSP. (To be defined).
3. etc...