Serial Communication between VME and DSP FPGA

 Communications from VME to the DSP FPGAs are accomplished in three steps:
  1. Send a 16-bit Frame to the DSP FPGA containing the command number and destination DSP
  2. Send the HI-order 16 bits (31-16) of the data word
    If bsel bit is set in FPGA control register only 30 data bits are used. Bits 31 and 30 are destination control:
  3. Send the LO-order 16 bits (15-0) of the data word
Note: the order of these steps is important.
See DSP FPGA Commands for more details.
Bits Name Description
Serial Frame Format (W/R)
8   Serial Data present and not yet read (R-only)
7-4   Command #
3-0   Destination DSP (4-0)
Serial Data (W/R)
16-0 DAT[15..0] LO order bits
16-0 DAT[31..16] HI order bits