Input FPGA Serial Commands

 The Input FPGA receives data from the hotlink receivers. Each Input FPGA deals with two hotlink channels (labelled A & B). Currently, A registers corresponds to even numbered channels (0,2...14) while B registers correspond to odd numbered channels (1,3...15).
After the input FPGA has received an entire event's worth of data on one input channel, it tags a trailer word (see below) to the end of that data and marks it with the complete flag (C-bit) used by the link.
See slic_rec.tdf for FPGA code.

Command # Data
A-Reg B-Reg Bits Function Value
Control Commands (R/W)
8 9 0 set/read RESET ERRORS 0
    1 set/read RESET EV_COUNT 0
    2 set/read RESET FIFO 0
    3 set/read TEST mode 1
    4 set/read HOTLINK RF 1
    5 set/read /EN_SDO_IN (B only) 0
    6 set/read ENDIAN 0=big
1=little
    7 set/read HOTLINK /BIST (A only) 0=BIST for A & B
Status & Errors (R)
0 4 0 read IDLE state 1
    1 read EVENT state 1
    2 read MISSING EVENT flag 1
    3 read END EVENT flag 1
    4 read FIFO /AF (almost full) 0
    5 read FIFO /FF (full) 0
Counters (R)
1 5 7-0 read ERROR_COUNT
counts RVS (err) in BIST mode		 count[7..0]
2 6 7-0 read EV_COUNT (lo byte)
counts data w/ no RVS (ok) in BIST mode		 count[7..0]
3 7 7-0 read EV_COUNT (hi byte)
counts data w/ no RVS (ok) in BIST mode		 count[15..8]
Test Data (W)
0 4 7-0 load TEST DATA byte 0 data[7..0]
1 5 7-0 load TEST DATA byte 1 data[15..8]
2 6 7-0 load TEST DATA byte 2 data[23..16]
3 7 7-0 load TEST DATA byte 3 data[31..24]
13 15 0 load LAST WORD flag 1
12 14 0 WRITE TEST DATA to FIFO 1