Output FPGA Serial Commands

 The SLIC output section consists of two FPGAs: the Output Buffer that receives data from the link and writes it to the output FIFO and the Hotlink Output that reads data from the output FIFO and writes it to the hotlink transmitter chips. The same data is copied to both the transformer coupled and non-transformer coupled outputs.
Serial communication is possible with the Output Buffer FPGA.
See out_buf.tdf and out_hlk.tdf for FPGA code.

  Data
Command # Bits Function Value
Control Commands (R/W)
8 0 set/read RESET EV_COUNT 0
  1 set/read RESET FIFO 0
  2 set/read RESET INPUT REG 0
  3 set/read RESET TEST DATA 0
  4 set/read TEST mode 1
  5 set/read RESET OUT HLK FPGA 0
  6 set/read ENDIAN 0=big
1=little
  7 set/read HOTLINK /BIST 0=BIST
FIFO Status (R)
0 0 read FIFO /AF flag 0
  1 read FIFO /FULL flag 0
Event Counter (R)
2 7-0 read EV_COUNT (lo byte) count[7..0]
3 7-0 read EV_COUNT (hi byte) count[15..8]
Test Data (W)
0 7-0 load TEST DATA byte 0 data[7..0]
1 7-0 load TEST DATA byte 1 data[15..8]
2 7-0 load TEST DATA byte 2 data[23..16]
3 7-0 load TEST DATA byte 3 data[31..24]
13 0 load LAST WORD flag 1
12 0 WRITE TEST DATA to FIFO 1