| Data | ||
| Command # | Bits | Function |
| VME Data | ||
| 1 | 15-0 | Lower bits (15-0) of the last data written from VME |
| 2 | 15-0 | Upper bits (31-16) of the last data written from VME |
| Input/Link FPGA Configuration Status | ||
| 3 | 0 | Link config busy |
| 1 | Link conf_done | |
| 2 | Link nstatus | |
| 3 | Input config busy | |
| 4 | Input conf_done | |
| 5 | Input nstatus | |
| Read Token | ||
| 4 | 1-0 | The token bits from write cmd number 7 |
| Serial Data from DSPs | ||
| 5 | 8 | Indicates that the serial word to be read with command 6 is valid and has not been read. | 7-0 | The serial frame received from the last DSP read. |
| 6 | 15-0 | Read lower bits (15-0) for extended 32 bit command. This clears the valid bit |
| 7 | 15-0 | Read upper bits (31-16) for extended 32 bit commands |
| Read Resets | ||
| 8 | 6 | The reset for the output FPGAs |
| 5 | The reset for the input and link FPGAs | |
| 4-0 | The dsp resets | |
| Input/Link/Output FPGA Serial Read | ||
| 9 | 8 | The data is valid from the input FPGA |
| 7-0 | The data received from the input FPGA | |
| 10 | 8 | The data is valid from the output FPGA |
| 7-0 | The data received from the output FPGA | |
| 11 | 8 | The data is valid from the link FPGA |
| 7-0 | The data received from the link FPGA | |
| Input/Link/Output FPGA Serial Busys | ||
| 12 | 0 | Input serial busy |
| 1 | Input serial valid | |
| 2 | Output serial busy | |
| 3 | Output serial valid | |
| 4 | Link serial busy | |
| 5 | Link serial valid | |