ADF to TAB Cabling

updated: 08-Jan-03

Index

ADF to TAB Channel Link Signal Assignments & notes
Cable/Connector Diagrams
Bit Stream Mapping on Channel Link Cable
TAB Sliding Windows Chip Input Channel Map

ADF to TAB Channel Link Signal Assignments

Relative TT [eta,phi]	ADF i-1 [out.chan]	Cable Pair [pair.bit]	TAB SW Chip [input]	ADF i [out.chan]	Cable Pair [pair.bit]	TAB SW Chip [input]	ADF i+1 [out.chan]	Cable Pair [pair.bit]	TAB SW Chip [input]
EM[0,0]				B.0	0.0	E:20	C.0	0.0	E:24
HD[0,0]				B.1	0.1	H:20	C.1	0.1	H:24
EM[0,1]				B.2	0.2	E:21	C.2	0.2	E:25
HD[0,1]				B.3	0.3	H:21	C.3	0.3	H:25
EM[0,2]	A.4	0.4	E:18	B.4	0.4	E:22	C.4	0.4	E:26
HD[0,2]	A.5	0.5	H:18	B.5	0.5	H:22	C.5	0.5	H:26
EM[0,3]	A.6	3.0	E:19	B.6	3.0	E:23
HD[0,3]	A.7	3.1	H:19	B.7	3.1	H:23

EM[1,0]				B.8	1.0	E:29	C.8	1.0	E:33
HD[1,0]				B.9	1.1	H:29	C.9	1.1	H:33
EM[1,1]				B.10	1.2	E:30	C.10	1.2	E:34
HD[1,1]				B.11	1.3	H:30	C.11	1.3	H:34
EM[1,2]	A.12	1.4	E:27	B.12	1.4	E:31	C.12	1.4	E:35
HD[1,2]	A.13	1.5	H:27	B.13	1.5	H:31	C.13	1.5	H:35
EM[1,3]	A.14	3.2	E:28	B.14	3.2	E:32
HD[1,3]	A.15	3.3	H:28	B.15	3.3	H:32

EM[2,0]				B.16	2.0	E:38	C.16	2.0	E:42
HD[2,0]				B.17	2.1	H:38	C.17	2.1	H:42
EM[2,1]				B.18	2.2	E:39	C.18	2.2	E:43
HD[2,1]				B.19	2.3	H:39	C.19	2.3	H:43
EM[2,2]	A.20	2.4	E:36	B.20	2.4	E:40	C.20	2.4	E:44
HD[2,2]	A.21	2.5	H:36	B.21	2.5	H:40	C.21	2.5	H:44
EM[2,3]	A.22	3.4	E:37	B.22	3.4	E:41
HD[2,3]	A.23	3.5	H:37	B.23	3.5	H:41

EM[3,0]				B.24	4.0	E:47	C.24	4.0	E:51
HD[3,0]				B.25	4.1	H:47	C.25	4.1	H:51
EM[3,1]				B.26	4.2	E:48	C.26	4.2	E:52
HD[3,1]				B.27	4.3	H:48	C.27	4.3	H:52
EM[3,2]	A.28	4.4	E:45	B.28	4.4	E:49	C.28	4.4	E:53
HD[3,2]	A.29	4.5	H:45	B.29	4.5	H:49	C.29	4.5	H:53
EM[3,3]	A.30	5.0	E:46	B.30	5.0	E:50
HD[3,3]	A.31	5.1	H:46	B.31	5.1	H:50

BX		5.2			5.2			5.2
Raw/Filt		5.3			5.3			5.3
Frame		5.4			5.4			5.4
Parity		5.5			5.5			5.5
unused	spare	6.0-5	n.c.	spare	6.0-5	n.c	spare	6.0-5	n.c
Clock		clk			clk			clk

Notes:

n.c. = not connected
TT Numbering
The 32 TTs seen by an ADF are numbered as two (EM and HD) 4x4 arrays in [eta x phi] with:
- eta: 0-3
- phi: 0-3
ADF Outputs
- Each SW chip on a TAB receives input from three ADFs.
- ADF outputs shown as blanks are not used by the TAB.
Cable Pairs
- Cable pairs numbered: 0-6 + clk
- Bits in each pair numbered: 0-6
  bit-6 used for DC-balance
Sliding Window (SW) Chip
- E = EM signal (0-80)
- H = HAD signal (0-80)
Parity
- Parity on each of the ADF's output cables calculated using only the data shown as used by the TAB
  (under discussion - may not be necessary)

Cables & Connectors

Connector Pinouts

Cable/Connector Diagram

Specifications

Cable: AMP 621410-4
Connector: AMP Z-Pack 2mm HM

Channel Link Cable-Pair Data Assignments

	Bit-Stream in Cycle
Cable Pair	0	1	2	3	4	5	6
0	0	1	2	3	4	5	DCBAL
1	8	9	10	11	12	13	DCBAL
2	16	17	18	19	20	21	DCBAL
clk	Clock
3	6	7	14	15	22	23	DCBAL
4	24	25	26	27	28	29	DCBAL
5	32	33	34	35	36	37	DCBAL
6	40	41	42	43	44	45	DCBAL

Notes:

See National DS90CR483 / DS90CR484, 48-Bit LVDS Channel Link SER/DES spec sheet

TAB Sliding Windows Chip Input Channel Map (EM & HD)

p h i	8	8	17	26	35	44	53	62	71	80
	7	7	16	25	34	43	52	61	70	79
	6	6	15	24	33	42	51	60	69	78
	5	5	14	23	32	41	50	59	68	77
	4	4	13	22	31	40	49	58	67	76
	3	3	12	21	30	39	48	57	66	75
	2	2	11	20	29	38	47	56	65	74
	1	1	10	19	28	37	46	55	64	73
	0	0	9	18	27	36	45	54	63	72
eta		0	1	2	3	4	5	6	7	8

Notes:

Each SW chip (j)on a TAB receives input from the following (in eta x phi space) for its 9x9 EM and 9x9 HD TTs
- ADF i-1: 4x2
- ADF i: 4x4
- ADF i+1: 4x3
- SW Chip j-1: 3x9
- SW Chip j+1: 2x9
Numbering Convention
SW Chip Inputs: 0-80