L1CAL & CAL-TRK LATENCY




updated Oct 26, 04















Step delta-t (clk) delta-t (ns) cumul-t (ns)
Notes
Bunch Crossing
0.0 0.0

Transmit to ADF




BC to ADF
650.0 650.0
measured - scope
sub-total
650.0 650.0

ADF CLK units (ns) 16.5

Calvet Mail - 25-Jun-02
Signal synchronization
91.0 741.0

ADC value valid 10.0 165.0 906.0

ADC pins sensed 0.5 8.3 914.3

Digital input decimated 5.0 82.5 996.8

Peak at convolver output 26.0 429.0 1425.8

Peak detect & dec. done 9.0 148.5 1574.3

Et LUT done 1.0 16.5 1590.8

Serial stream selected 1.0 16.5 1607.3

Delay adjustment 0.0 0.0 1607.3

Parity calc / 8-10 bit select 1.0 16.5 1623.8

FPGA out valid - ser clk 0.5 8.3 1632.0

LSB of chan at TAB 3.0 49.5 1681.5

MSB of chan at TAB 7.0 115.5 1797.0

sub-total
1147.0 1797.0

TAB CLK units (ns) 11.0


SW Chip Input



need to check code
Resynch inputs 12.0 132.0 1929.0

Parity,etc. 2.0 22.0 1951.0

Data to/from neighbors 1.0 11.0 1962.0

Test/Data mux 2.0 22.0 1984.0

Measurement



made 07/10/04
Algo In to SLDB In
450.0 2434.0

SLDB




transmitter in to out
90.0 2524.0
K.Johns - 26-Aug-02
sub-total
727.0 2524.0

CAL-TRK



K. Johns 01-Aug-02
Deserialize
40.0 2564.0
TDR - meas w/o 250 ns cable
8b - 10b decode
50.0 2614.0

DAV to FF MT
40.0 2654.0

FF MT to start processing
19.0 2673.0

Start proc to FB data
56.0 2729.0

FB data to avail (+MTC05)
396.0 3125.0
MTC05 tri logic - 132 ns
Data avail to data ready
38.0 3163.0

extra
90.0 3253.0
assumes no MTM for Cal-Trk
sub-total
729.0 3253.0

TOTAL

3253.0

TFW decision due (Run 2a)

3300.0

Difference

-47.0

TFW decision due (Run 2b)

4092.0

Difference

-839.0