Subject:
Re: parity test results
From:
Jovan Mitrevski <jmitrevs@phys.columbia.edu>
Date:
Thu, 16 Oct 2003 14:39:04 -0500
To:
Jovan Mitrevski <jmitrevs@phys.columbia.edu>
CC:
parsons@nevis.columbia.edu, Hal Evans <evans@nevis.columbia.edu>,
ban@nevis.columbia.edu

Jovan Mitrevski wrote:

Hi,

Here is a summary of our parity tests:

1. Out of the 4 cables, one is bad, or its connectors are bad. Parity
   errors followed the cable as we moved it at both the ADF and the
   TAB.

2. For pseudo-random data (not sure if the ADC's were on), we had
   error-free transmission (except on the bad cable) for 15
   minutes. Then all the inputs, including the input from the
   testboard, experienced a parity error. I don't know the
   reason. After a few more minutes running, there were no more
   errors.

3. With all the ADC's on, looking at raw ADC counts, one cable
   experience a parity error rate of a few hertz. From what Denis
   tells me, there were no errors when ADC number 16 was turned
   off. Also, ADC 16 by itself produced no errors. It had to be on
   along with a certain number of other ADCs before errors started
   appearing.

Denis says that it would be really important for next time to have
parity error counters, and not the 2-bit saturating ones I suggested,
but 16 or 24 bit saturating ones. He suggested 24 bit as being better,
because it takes 2 seconds to saturate it, while a 16 bit one
saturates in some miliseconds, but a 16 bit one fits into our 16 bit
readouts easier. It would be good to add one of these counters to each
of the cable buffers and to add it to the address space of the TAB so
that we could read it out. The stratix status could remain the same,
though we should still fix the status information that gets sent to
chip 10 to send the correct parity error result.

Jovan