Subject:
VRB captured header and vertical parity!
From:
Jovan Mitrevski <jmitrevs@phys.columbia.edu>
Date:
Wed, 24 Mar 2004 22:43:59 -0600
To:
Jovan Mitrevski <jmitrevs@phys.columbia.edu>
CC:
Hal Evans <evans@nevis.columbia.edu>, John Parsons
<parsons@nevis.columbia.edu>, Chad Johnson
<cjohnson@nevis.columbia.edu>, Jaroslav Ban <ban@nevis.columbia.edu>

Hi,

After nicely reseating the bit3 card in slot 0, removing the bit3's
memory, and carefully adjusting the TAB power supply, I was able to
get nice, stable behavior with the setup. Therefore, I proceeded with
the tests, one more time, and this time we have some success! The VRB
receives the header, all zeros for data, the vertical parity, and the
zero pading at the end. I actually feel pretty good about this because
I think the zeros are just a firmware bug. I also get zeros captured
in the chip10 raw memory capture. At Nevis the environment is
different with 32 bunch crossings per turn and a pulse and init
occuring every single turn on the same bunch crossing, and apparently
I didn't exercise this bug.

For debugging this, I probably need a ByteBlaster (MV or II) and some
time to fuss with it. I saw a ByteBlaster MV in MCH2 by the STT
crates. Is that a Columbia ByteBlaster that maybe I can use? I am also
busy trying to get data for my CALGO talk on Tuesday, but there should
be enough time for both.

Anyway, I should now head back to Chicago so that I can try to get 6
hours of sleep before coming back out for the 8am meeting.

Jovan