********************************
		    L1CAL SYSTEM BASELINING STATUS
                   ********************************

updated: 20-Jun-02

SCHEDULE
========
12-Jul        Critical tech decisions made
29-Jul        Baseline Frozen
	      - TDR submitted
              - All WBS doc's ready
	        Schedule,Cost,Contingency,Risk,BoE, etc.
week 12-Aug   Temple-style review (pre-baseline)
week 26-Aug   Lehman review (baselining)


SYSTEM COMPONENTS FOR BASELINING
================================
*  = task needs to be be defined
** = critical technical decision needs to be made

I: ADF (ADC-Digital-Filter)
---------------------------
 1) Crate/Backplane
    a) crate+power:     Wiener 6023 (6U)
**  b) backplane I/O:   connector or transition card
 2) In-crate Processor
    a) VME interface: SBS/Bit3 VME-PCI interface
 3) Algorithm
    a) Matched filter + peak detector
       (does this fulfill the latency requirement?)
 4) Output to TAB
    a) LVDS with Channel-Link mux
    b) duplication (2-fold) of data done at ADF output
    c) data: 8-bit per TT
*   d) synch/timing/error signals to be decided
 5) Output to L2/L3
    a) no path to L2/L3 from this board (???)
 6) Downloading
    a) download path: over VME - control by CPU interfaced to COOR
*   b) data:          produce list of data to download
 7) Monitoring
*   a) method of recording inputs
 8) Testing
    a) Analog Splitter


II: ADF Timing Board
--------------------
 1) Source of ADF timing information
**  a) GAB or separate card
 2) Signals Required
*   a) specify SCL signals needed


III: TAB (Trigger Algorithm Board)
----------------------------------
 1) Crate/Backplane
    a) crate:     9U VME
**  b) backplane: custom backplane to be decided
 2) In-crate processor
    a) commercial VME cpu to control downloading, monitoring, testing
 3) Input from ADF
    a) LVDS with Channel-Link demux
    b) duplication (2-fold) of data done at ADF output
    c) data: 8-bit per TT
*   d) synch/timing/error signals to be decided
 4) Algorithm/Architecture
**  a) Sliding Windows algorithm: 
       RoI size (2x2 or 3x3), Declust region (3x3 or 5x5 RoIs)
**  b) Data per Board:
       slice in eta or in phi
 5) Output to GAB
    a) data format:                specified
**  b) output medium:              to be decided
*   c) synch/timing/error signals: to be decided
 6) Output to Cal-Trk
    a) data format:   specified
    b) output medium: UAz Serial-Link-Daughter-Board
 7) Output to L2/L3
    a) data format:   preliminary specification
    b) output medium: G-Link (fiber) 
 8) Downloading
    a) download path: over VME - control by CPU interfaced to COOR
*   b) data:          produce list of data to download
 9) Monitoring
    a) collect information over VME - control by CPU interfaced to ???
*   b) data: produce 1st pass list of things to monitor
10) Testing
*   a) basic scheme: define this


IV: GAB (Global Algorithm Board)
--------------------------------
 1) Division of Tasks
**  a) SCL and Sums/output to TFW on same or different boards
 2) Input from SCL
    a) use SCL mezzanine
 3) Algorithms
    a) Final summing: description
*   b) Trigger Terms: 1st pass list
 4) Ouput to TFW
    a) data format:   understood (triggers to be defined later)
*   b) output medium: to be understood
 5) Output to L2/L3
    a) data format:   preliminary specification
    b) output medium: G-Link (fiber) 
 6) Timing/Control Output (to TAB)
**  a) signals:       to be decided
**  b) output medium: to be decided
 7) Downloading
    a) download path: over VME - control by CPU interfaced to COOR
*   b) data:          produce list of data to download
 8) Monitoring
    a) collect information over VME - control by CPU interfaced to ???
*   b) data: produce 1st pass list of things to monitor
 9) Testing
*   a) basic scheme: define this


V: LATENCY
----------
 1) Latency Budget  (ns)
**  a) Need to have this budget balance

    BC to ADF        650
    ADF to TAB       990
    TAB to Cal-Trk  1499
    Cal-Trk to TFW   544
                    ----
    Total           3683

    TFW decision    3300
    Difference       383 (!!!)