RUN 2B L1CAL MEETING MINUTES
			     22 August, 2002


Hal Evans		      Report from the Temple Review
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o See Hal's slides linked off of the agenda for details


All			      Status Reports
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o Nevis
  - A first layout of the input portion of the TAB has been done
    . assuming 3 input cables from each ADF
  - transmission ADF-to-TAB (comments from Denis)
    . ideas on how to do splitting of signals on backplane
    . jitter: found new chip <100ps
    . space:  use TABs in every other slot liberates space for chips
    . power:  found lower power chip
    . Denis will send mail to Nevis with the details
  - Next task will be to build some test-boards to check that signal
    transmission using the proposed cables and the Channel Link
    transmitters/receivers works correctly
o Saclay
  - received splitter pcb's & components
  - freezing FPGA pinouts for ADF boards
  - after this
    . inteface for download
    . then schematic
  - another engineer designing SCL fanout card
    . going well
  - 1 crate ordered
    . delivered in Sep/Oct
  - FPGA demonstrators ordered
    . arrive in a few weeks
  - no progress on ADF-to-TAB cables
  - will need to get Bit3 and VME vertical-interconnect soon
    . necessary for design of custom backplane
    . mid-Oct
o Monte Carlo
  - 4e32 @ 396ns generation w/ new SMT geometry
    . WH --> munu bb + 12-15 minbias
    . probably will not have more than this
  - need to check that L1Cal is insensitive to no. minbias
    . check 1-jet rates for 0.5, 5(?), 7.5, 10 minbias
    . Jovan will do this at Nevis