RUN 2B L1CAL MEETING MINUTES 03 October, 2002 Hal Evans Lehman Post-mortem --------- o In general, the trigger part of the review was a big success . committee recommends that we're ready for baseline approval . we were complimented by both the committee and the DOE on the thoroughness of our documentation and preparation > thanks to all who helped out here! . the Closeout Report from the committee will be available soon. o Final Baseline Approval (release of money) has to wait though . at least until after the DOE review of the Tevatron accelerator in late October - early November . perhaps even longer than this . the committee was a big help here in pointing out to the DOE that we need money now o There are also a few administrative things the committee recommended that we change before submitting out baseline to the DOE a) decrease (!) the level of contingency throughout the project > note: we were able to convince the committee that no such changes should be made to the L1Cal contingency (at least they were convinced last time I checked) b) increase the amount of time in the schedule > this was mainly aimed at Silicon, where the committee felt that the schedule was overly aggressive. The suggestion was to move the "silicon ready" date by about 9 months (I may be remembering this incorrectly though) > however, even if we leave the trigger schedule unchanged, movement in the silicon schedule will move the date at which we need to be installed. o Options for increasing length of schedule in L1Cal a) increase the amount of time in the prototype and pre-production integration steps by a factor of 2 b) add a period of "running in parallel" with the Run IIa trigger system after L1Cal production is complete > to do this we would need to produce enough splitters to instrument some sizable part of Run IIb L1Cal - perhaps one quadrant. c) other suggestions of things to do here would be most welcome... o Caveats for running in parallel - Philippe: no room in counting house for an extra parallel system . would have to come up with some creative solution - Denis: splitter is designed for just a few channels . there will be a problem of space/power if many channels are needed . also money will be an issue Denis Calvet Status of ADF System Design ------------ o Analog Splitters - Tests: start in Oct. . need BLS/CTFE cables (~10cm & 5m) . have one cable now: but 80-100 m long . have to ask Dan about this - still on sched for Feb even if need another iteration o ADF Board - Core FPGA: vhdl 100% complete & sim . 8 channels in XC2V500 (-4 = slowest) - VME interface & bootstrap = 100% - Board level sim: started . 4 cor fpga's + vme + bootstrap o VME Interface / Bootstrap - A24/D16-D8 VME slave - no interrupts - 4 fpga's config loaded by vme - SCL_init . used to restore event synchronization - not to restore filter param's/fpga code . received from SCL mezzanine card . ADF algorithm is deterministic - so this can't be stuck o ADF Crate - J2 = custom (passive) backplane (design not yet started) - J0 = cables to TAB - crate to be delivered 20-Nov o Power Estimation - per crate totals . +5V: 45 A . -5V: 12 A . +3.3V: 60 A - overvoltage protection for adc's 3.3V . use crate power supply - but no explicit protection . need to think about this o Timing Card - fan out signals from SCL mezzanine card . connections in LVDS - design in progress - no room in ADF crate . use back of slot-0 in ADF crate? > need to check on space - conflict w/ vertical interconnect card? > prefer not to use embedded processors - more complicated . space in TAB crate? > physical space exists o High Speed Links - Format (36 bits out of 48) . 32 data . 1 start of frame . 1 length of frame (8 or 10 bit) > xfer raw ADC samples on L1 trigger . 1 flag BX (send BX count) > send BX and TURN on L1accept . 1 parity bit o Test Bench ADF Board - probably redundant w/ Nevis cable tester - could ship a Nevis test board to Saclay - also need a PCI-to-VME interface . none unused interfaces available at Fermilab o Software - ADF crate address map: use full 16MB A24 space . ==> need 4-5 16MB windows in TCC - Questions: . OS, language, libraries, application? . note: TCC is the only online computer in D0 that uses Windows > may want to switch for Run IIb > Win 2k and Win NT are the same as far as TCC is concerned . C++ is prefered language, but C is ok as well o Short Term plans - test analog splitters: 1 week - ADF board sim - power supply circuit for ADF - start ADF schematic capture Hal Evans Status of Design at Nevis --------- o Trigger Algorithm Board - Done: . Jet, EM and tau algorithms coded and simulated in Stratix fpga . layout of two input sections > this was considered prudent to try because of the high density of signals required in these sections - To Do: . finalize ADF-to-TAB protocol > Denis' scheme above is a good starting point . firmware for Global chip: receives results from all Sliding Windows chips . all output sections: L2, Cal-Trk, Monitoring, etc. o Global Algorithm Board Status - detailed design will begin when TAB design finished o ADF-to-TAB High-Rate Transmission test system - Having a working model of this is vital since it drives the design of the system. - We have just designed and fabricated such a test system . finished the first board on Monday, 30-Sep - Functionality . Transmitter and Receiver sections on same PCB, but with different ground planes and power . Transmitter and receiver fpgas with clocks separate from data transmission clock > Altera APEX chips > format data for transmission > buffer received data and check for transmission errors > system controlled using Quartus software . Channel-Link 48-8 transmitter and receiver with tunable transmission frequency > identical to what is proposed for final system . 5 m cable connecting transmitter to receiver > AMP with 2 mm hard-metric connector > identical to proposed cable - First tests of system . all channel-link parameters tried > transmission frequency, voltage overdrive, dc-balance, deskew option . no obvious problems found - More thorough tests will now start . systematically explore full parameter space - Note: bit error rate spec for these chips is 10e-12 Any Other Business ------------------ o Next meeting in two weeks - should discuss details of ADF-to-TAB data transmission scheme > protocol, data duplication, etc...