RUN 2B L1CAL MEETING MINUTES
			     9 January, 2003

Present
o MSU:		M.Abolins        
o Nevis:        H.Evans, J.Mitrevski, J. Parsons
o Northeastern: D.Wood
o Saclay:       E.Perez,J.Bistricky, D.Calvet


L1Cal Simulation Issues: Emmanuelle Perez
------------------------

o Resuolution and Noise for TT signals
  - L1Cal examine --> resol & noise of current system
  - Check whether res in simulation is realistic
  - Vary these parameters
    . prelim studies ==> no big effect (b/c of digi step)

o Performance of Digital Filter
  - using Denis' standalone program
  - Check that <Et(tot)> = 0
  - Check for loss of signal peak in presence of pileup

o Algorithm Studies to do
  - ICR
    . need new MC files with p13
      > also useful for tracking
  - Tau
    . release this next week
  - Cal-Track matching
    . tsim_l1cal2b ==> trig jets chunk
    . does L1CTT do the same
    . if so, this is easy
  - Topological Studies
  - Note: all important for and/or term production
    . see web page w/ preliminary list
      > http://www.nevis.columbia.edu/~evans/l1cal/hardware/
               trig_terms/trig_terms.html
      > let us know asap if you have other ideas
      > this will impact the TAB/GAB design

o MC p13 Production Organization
  - nothing yet - but we will need to request this
  - need to produce a list of processes that we need
    . each group should produce a list be next week Thurs and submit
      to Emmanuelle 


ADF Simulation: Jiri Bistricky
---------------

o Denis' Simulation program
  1) Pattern Generator
    . generate amplitudes with noise
    . assign to different BC's
    . many different ways to 
  2) Filter
    . filters higher frequency comp from patt gen
  3) Sampler
    . this is the ADC
  4) Filter - Peak Finder
    . same as 2) but used as peak finder

o Jiri's first attempt at using this
  - has generated 1000 pulses separated by random number of BC's
    . Min sep = 4 BC's
  - found peaks for ~2/3 of pulses
    . found all pulses with >4 BC separation from next
  - need to tune parameters/coeff's to improve this


Saclay Design Status: Denis Calvet
---------------------

o Drawing schematics of ADF boards
  - all components chosen
  - should be verified in a few weeks (2 weeks)
    . end of ADF proto design

o PCB design
  - start before end Jan 1.5-2 weeks from now
  - takes 3-4 weeks ==> mid-end Feb

o Bit3 Interface received at Saclay
  - starting to install drivers - some problems

o Splitter at Fermilab
  - shipped Dec 20 to Dan at MSU
    > received
  - current plan: Dan is supposed to test/install this
    > should be sent to Fermilab next week
    > it is crucial that these tests are done quickly to allow us to
      proceed with the plans for parallel integration



Nevis Design Status: Hal Evans
--------------------

o Peak Finding Problem
  - see 12-Dec-02 meeting for details of the problem
  - sending peak bits on "spare" cable pairs will not work as a
    fallback solution
    . spare lines may not be connected at TAB
      (working on this)
    . would cause the loss of at least on BC tick to include this
      information with the TT Et's
      > this would break the latency budget for transfer to Cal-Track
  - will have to use 9-bit transfer as the fallback
    . probably enough resources in ADF FPGA to do this

o Layout of Input section progressing well
  - uses up *all* the space on the back of the board
    . very dense
  - ==> no standard backplane possible for TABs
    . only power

o Layout depends heavily on Cabling Assumptions
  - check cabling web page for details
  - http://www.nevis.columbia.edu/~evans/l1cal/hardware/
           cabling/adf_to_tab_cable_map.html
  - cable shielding: this should be tied to ground
    . Vince Pavlicek asks whether this will cause ground loops
    . note that center pins of cable are tied to ground
      > the shield shouldn't add to this
    . need to check this further
  - Should we produce an Approved Cabling Document?
    . probably yes - Hal will take care of this

o Communication with TAB/GAB by VME
  - Proposing a dedicated board (or section of GAB) to interface VME
    to TABs/GAB
    . uses a fast serial protocol
  - Firmware downloading
    . all TAB firmware for all boards downloaded in ~30 seconds
  - VME readout
    . transparent way of doing this given that no standard VME
      backplane possible for TABs
  - Open question: where does this sit
    . part of GAB: 
      > more economical use of boards?
    . Separate Board
      > largely decouples GAB from TAB testing

o Crate Issues
  - Need 2 slots for each TAB to be able to cable them
  - Not a lot of room in crate for extra cards
    . may want to take VME functionality out of TAB crate altogether
  - Does ADF SCL interface need a home?
    . prefered solution: put it in the back of slot-1 of ADF crate
    . should we foresee a dedicated VME crate to house?
      > TAB/GAB VME interface
      > ADF SCL interface