RUN 2B L1CAL MEETING MINUTES 3 April, 2003 Present o Fermilab: G.Cancelo, J.Kotcher, V.Pavlicek o MSU: M. Abolins o Nevis: H.Evans, J.Mitrevski o Northeastern: D.Wood o Saclay: J.Bystricky, D.Calvet, P.Demine Status from Saclay: Denis Calvet ------------------ o ADF Layout - still continuing: finish by end next week - started to contact companies for production of 2 boards - should be able to start PCB production in mid-April - Tests should be able to start in beginning of June - Ship board to Fermilab by end July / beginning of August . Denis will be Fermilab during end August o Analog Splitters - produce 3 more of these - some minor mod's to these: start after ADF layout done - ship to Fermilab: mid-end June o Cable Harness - BLS cables will enter ADFs via a cable harness . will not require re-routing BLS cables --> simplifies installation - connectors ordered . ERNI, TYCO (US) - cable . also exploring US companies - need to know lengths of these cables . will require 5-10 km of this cable . need to store/put connectors on these > haven't identified someone to do this production - will ship this along with ADF board o Control Interface - SBS VME-PCI interface (616) has finally been repaired but will take 2-3 weeks to ship . software development can start mid-end April . perhaps can get a loan of one of these from Fermilab - another possibility: VME Single Board Computer . have one at Saclay now - Will either use SBS PIC-VME or SBC for integration test . need to get infrastructure at Fermilab set up for this o SCL Interface - not going as quickly as expected . engineer only working part-time . not familiar with VHDL design - Standard SCL interface . 6U board mounts on back of crate in slot 1 . 6 outputs (4 for ADF crates + 2 spares) - considering a backup solution . make a simpler board: small mezzanine card with 1 output . plugs on Virtex II evaluation kit > 1M gate FPGA > 2 18-pin connectors . need to include connection for SCL mezzanine card - Denis has started work on this mezzanine card . more news by end of April - Could also (in parallel) pursue option of using TAB/GAB VME/SCL Interface signals . may require cable adapter . possibly require 8-bits of BX-related information > this may not be absolutely required for summer tests - seems sensible to divert engineer working the SCL interface to work on splitter . means we would use Nevis VME/SCL interface for timing signals for the ADF . this frees up some of Denis' time for other things o Software - test software for ADF board started . interfaced to simulator . can be used for tests of multiple ADFs . will serve as base for final system software . multi-thread application (keyboard, TCP/IP inputs) - MSU will start interfacing this software to TCC software . communication done via TCP/IP socket . all comm. in ascii format Status from Nevis: Hal Evans ----------------- GAB Changes: o Have settled on splitting the old GAB into 2 9U boards - VME/SCL Interface: VME and SCL functions (required for tests) - GAB: trigger functions (not req. for tests) o VME/SCL Interface is the combination of the separate VME and SCL interfaces presented at the last meeting - see PMG presentation linked off "hardware page" http://www.nevis.columbia.edu/~evans/l1cal/hardware/hardware.html - managed to fit this all on a 9U board o Some VME/SCL Details - 9 banks of LVDS outputs . 6 pairs VME + 6 pairs SCL - VME communication to TABs and GAB will be (initially) slower than standard VME . VME part of LVDS runs at 15 MHz . can be optimized later - SCL signals . clk7 either SLC 7MHz clk or local oscillator . init SCL init request or init requested thru VME . turn SCL FIRST_PERIOD - used for internal BX & TURN counters . l1_accept from SCL . pulse used for triggering via VME flexible definition of timing of triggers can be used in both "run" and "test" modes . spare o Status - design: done - schematics: done - layout: done in a few weeks TAB Status: o Still in layout of TAB - estimate completion in 2-3 weeks o Have added/streamlined on-board monitoring capabilities - will make testing of TAB much easier - had an impact on the layout o After layout finished need to independently check all connections - making modifications after board is built will not be possible - using BGA's for 11 main chips (Stratix) on the board . 10 Sliding Windows . 1 Global chip Noise Studies: Jiri Bystricky ------------- o Dan has sent a few of the noise spectra to Jiri - 1 EM tower + 1 Had tower (directly from BLS cables - no splitter) - 4 ns sampling o EM Noise - RMS ~ 0.09 GeV . normalization 62 GeV = 2 V (central TTs) - After Analog Filter: RMS ~ 0.07 GeV . max < 0.25 GeV o Had Noise - RMS ~ 0.065 GeV - After Filter ~ 0.060 GeV o Amplitude Correlations - see correlation at BC frequency (7.59 MHz) in EM signals . much less corr. in Had signal o Conclusion - if all TTs behave this way ==> no problem with noise after analog filter - need to check other TTs: Dan will send more soon Trigger Towers with Splitter: Pavel Demine ---------------------------- o Compare Same TTs with and without splitter installed - ieta = -9 - 12, iphi = 1 o EM - changes are small o To Be Continued next Meeting Discussion: ---------- o Online System - Darien and Philippe have started discussions . will distribute a proposal when this is more advanced o Saclay hardware web page created by Emmanuelle - http://www-clued0.fnal.gov/~perez/R2BTRIGGER/ADF_Description/ ADF_Descri.html - will be linked off L1Cal Hardware page o Plans for integration period - shutdown scheduled for 6 weeks starting in mid-July . start date could conceivably slide . Jon will push for a firm date - Dan needs to be available during this time - someone from Columbia can be there for ~the full time - Saclay . Denis at Fermilab for 2-3 weeks at end-August . Patrick, Emmanuelle at Fermilab for Lepton/Photon (7-16 Aug) - lists of requirements from Saclay and Nevis for this test . Denis has produced this list . Hal will produce one soon