RUN 2B L1CAL MEETING MINUTES
			     17 April, 2003

Present
o Fermilab:     G.Cancelo, J.Kotcher, R.Partridge, V.Pavlicek
o MSU:		M. Abolins, P.Laurens
o Nevis:        H.Evans, J.Mitrevski
o Northeastern: D.Wood
o Saclay:       P.LeDu, E.Perez



Status from Saclay: message from Denis Calvet
------------------

o ADF Card
  The layout of the ADF card is still under way, this task was indeed
  much more complex than we anticipated. After routing ~70% of the
  signals we were confident that the design would fit on a 10 layer
  class 6 PCB, but we were forced to go to 12 layers last week and now
  have 14 layers. Now, 90% of the signals are routed - but there are
  still areas that may cause difficulties. Changing the numbers of
  layers implies to change the thickness of the boards, hence
  re-calculated the width of all controlled impedance traces, so the
  schedule has significantly slipped. I hope that the layout can be
  completed by the end of April, but given that it takes at least 6
  weeks to produce the PCB and assemble the card, we are now starting
  to eat the time foreseen to test the board (June).
  - Still hope to have the board at Fermilab in time for mid-August
    installation. 
  - Try to come up with contingency plan for testing at Saclay
    . current plan is to test ADF at Saclay until Denis leaves on
      holiday 
    . note Denis goes on holiday 3rd week of July - mid-August

o Cables & Connectors
  I received the connectors I intend to use at the back of the ADF
  crate (on J2), but these slightly protrude on J0 so that the cable
  from the SCL distributor interface may not be plugged on its ADF
  card. We will change the design of the PCB to move up all HM cables
  on J0 (I had one row of GND between each cable for shielding - this
  will be suppressed to gain 6 mm).

o PCI-VME Interface
  I also got back the Bit3 PCI/VME interface. I started
  to play with it and it seems to work.

o SCL Interface
  We put a lower priority on the SCL interface, but we
  are still working on it when no higher priority task has
  to be done.



Status from Nevis: Hal Evans
-----------------

o VME/SCL Interface
  - board submitted to the fabricator

o TAB
  - Layout essentially done
  - In process of doing independent check of layout
  - Will submit board next week

o Cables and Connectors
  - Have found nice shrouds and latches for ADF-to-TAB cables (AMP 2mm
    HM cables and connectors) 
  - Checking with Denis to make sure our cable assumptions are all
    consistent 
  - Will post the latest cable information on the web soon
  - May have substantial savings if we order all ADF-to-TAB cables and
    connectors now
    . getting quotes for this now
    . note that we have already verified experimentally that the
      cables will run at significantly more than the required data
      rates 


Discussion of Data Pump
-----------------------

o See "Questions from Vince" and "Thoughts from Denis" linked off the
  agenda page

o Additional Questions
  1) What is input impedance of ADF boards
     - BLS cables are 80 Ohms - may be modified by cable harness?
  2) Low pass filter on Data Pump: what should its characteristics be?
     - ADF: 7.5 - 15 MHz
     - suggestion to roll off Data Pump at 30 MHz
     - should this be reduced to <15 MHz so as not to introduce
       spurious high-f noise
  3) 1-ADF worth of output channels in Data Pump
     - delays between individual outputs?
     - there are compensated grossly using the cable harness
     - also possible to shift channel-by-channel timing in the ADFs
     - delays in data pump would allow to test ADF timing correction
  4) Necessary to have very different analog signals (wave shapes)?
     - different amplitudes is easy
     - different wave shapes would require a separate DAC for each
       channel
  5) Output: is it analog differential?
     - yes, BLS is 6V differential

o Goals for Data Pump
  - produce large numbers of test inputs
  - run independently of D0 and/or Cal data
  - test for cross-talk on ADF
  - loop mode of operation: high rate for long periods
    . probably not possible using ADF or TAB test memories
  - Timing Connections / Commands
    . needs to have SCL connections
    . also should have option of using local clocks
    . how much VME control of this board is necessary/useful

o To Do
  - Vince's group will produce a block diagram and distribute it to
    the group 



Any Other Business
------------------

o IEEE meeting in Montreal
  - We have 2 D0 talks:
    1) D0 Run IIb Upgrade (including silicon)
    2) Run IIb L1Cal - Denis will give this
  - We need to find someone for talk 1)
    . send suggestions to Patrick and Hal