RUN 2B L1CAL MEETING MINUTES
			     26 June, 2003

Present
o Fermilab:     G.Cancelo, V.Pavlicek, S.Rapisarda
o MSU:		
o Nevis:        H.Evans, J.Jin, J.Mitrevski
o Northeastern: 
o Rice:         P.Padley
o Saclay:       J.Bystricky, D.Calvet



Status of the Test Waveform Generator: Stefano & Gustavo
--------------------------------------

o Harware (2-channel test system)
  Card-1
  a) Xilinx test card
  Card-2
  b) DAC
  c) AD8138 (Amp/Filtering)
     . Gustavo working on this now
     . 2-3 weeks more of work

o Software
  - Stefano working on user-friendly interface for Xilinx card

o Work proceeding well
  - could possibly have this ready for July - certainly for August


Status from Sacaly: Denis Calvet
------------------

o ADF board not yet back from assembler
  - probably delivered next week (when Denis is on vacation)
  - testing will start on 15-July

o Suggest to postpone August integration by ~1 month
  - to end September or October
  - could this be sped up using more resources?
    . probably not on hardware 
      > no people at Saclay available in the next 10 days
    . develop software could be a possibility
      > need ModelSim VHDL simulator + Xilinx software + Visual c++
      > Denis can send all VHDL and c-code source
      > will send all the necessary files to Hal

o Cable Harness
  - all component ordered
  - delivery date beginning of July
  - cable delivery is late - Denis is checking on it w/ company
    . not critical to 

o SCL Mezz card
  - schematic finished
  - will start layout on 7-July
    . should tak 2-3 weeks
    . could be in production in beginning August
  - if integration is postponed - could have this card ready

o Other Mezzanine Cards
  - reduced version of ADF: 1 channel no digital output
  - channel link tester: 1 receiver 
    . 2K memory
    . error detection
  - design/schematics done
  - layout after SCL-mezz. (1st channel link tester)


Status from Nevis: Hal Evans
-----------------

o TAB
  - 1st TAB prototype recieved back from assembly on 24-June
  - Tests completed so far:
    . powers up OK: 6V & 48V distrib correctly through DC-DC converter
    . VME access through VME/SCL works
    . can download firmware to all Sliding Windows Stratixes
      > test memories written/read through VME/SCL
    . timing signals successfully received/locked from VME/SCL
  - Next step
    . load test memory with events - spin through SW chips


Any Other Business
------------------
o Hal will be at Fermilab next week
  - let him know if you have any requests for integration test setup