RUN 2B L1CAL MEETING MINUTES 10 July, 2003 Present o Fermilab: V.Pavlicek, S.Rapisarda o MSU: M.Abolins o Nevis: H.Evans, C.Johnson, J.Mitrevski o Northeastern: D.Wood o Rice: o Saclay: Status of the Test Waveform Generator: Stefano Rapisarda -------------------------------------- o Making good progress on work described in last meeting o Should finish this by next meeting Status from MSU: Maris Abolins --------------- o Philippe now has the new L1TCC computer and is working on it - will use Linux as the OS (rather than Windows) Status from Nevis: Hal and Jovan ----------------- o TAB - testing of the TAB prototype is proceeding smoothly - no problems found so far o Integration Test - John and Jovan will come to Fermilab from 28-31 July to do 1st stage of the test Integration Test Discussion: all --------------------------- o 1st Stage: test VME/SCL-to-SCLHub connection - set up test system infrastructure . collection of system infrastructure hardware going well . still looking for 3.3V and 5V power supplies for VME crate - synchronize to 7 MHz clock from SCL - correctly interpret SCL data (e.g. see SCL Init signal) o 2nd Stage: test TAB-VME/SCL-SCLHub - will wait to bring TAB out to Fermilab until it is "fully" tested at Nevis . "fully" tested means that TAB receives data from Channel-Link transmitter test board (used previously to test Channel-Link chips and LVDS cable) and pushes it through to the output of the Global chip on the TAB - if things continue to go as smoothly as they have been so far, this "full" test should be accomplished by mid-August o 3rd Stage: test ADF-TAB-SCL - ADF crate for this test is now in customs - will try to put this into the rack in the Test Area and set up power and monitoring as soon as possible Any Other Business ------------------ o We will have a detailed discussion of the Integration Test in the next meeting (24 July). Please try to attend so that we can get as much input as possible.