RUN 2B L1CAL MEETING MINUTES 24 July, 2003 Present o Columbia: J.Jin, C.Johnson, J.Mitrevski o Fermilab: D.Edmunds, V.Pavlicek o Maryland: D.Baden, + o MSU: P.Laurens o Nevis: H.Evans o Northeastern: D.Wood o Saclay: D.Calvet, E.Perez o Virginia: B.Hirosky Discussion of ADF Technical Design ---------------------------------- o Discussion guided by Denis' presentation at the November Saclay workshop - Meetings --> 2002 --> 4-6 November o ADF Crates: 6U Wiener crate w/ VME-64 backplane (slide 44) - standard VME64x backplane . use 5V, 3.3V, geographic address and all reserved lines - A24/D16 or D8 - analog I/O over J2 using Cable Harness - digital I/O over J0 (HM connectors) - ADF I/O . 32 input channels . 3 outputs to TAB . one card will receive SCL signals and fan them out >using reserved bus pins on J1 o ADF Algorithms (slide 5) - four 500,000 gate Virtex II FPGA on each ADF . XC2V500 FG456 -4 C . ~50% RAM and 80% logic used o Analog Splitter (slide 7) - one already installed - will produce 3 more . --> 32 analog channels available - Test Waveform Generator being developed at Fermilab . allow o ADF Board Block Diagram (slide 10) - VME interface in Cypress chip - with prom & 64MHz osc. - CPLD-flash memory (programmed via JTag) connected to VME bridge used to program 4 FPGAs (FPGA Programmation Interface) - Power . 5V - for logic and analog (from backplane) . 3.3V - for ADC (from backplane) . 1.5V - FPGA core (DC-DC conversion) . 3.3V - for logic (DC-DC conversion from 5V) - FPGAs 0-3 - FPGA output to 3 Channel-Link serializers . each output gets identical data (32 channels) . each output on 7-pairs --> J0 . 36 streams used (see hardware/cabling/adf_to_tab_cable_map.html on web) > 0-31: 32 analog channels > 32: parity > 33 BX counter > 34: frame bit (LSB marker) > 35: frame 8/10 bit - used to distinguish b/w sending filtered or raw data - Analog Input . Z-DAC: used to adjust pedestal (0-level) on each input channel o Analog Section (slide 11) - ADC: Analog Devices 9218 . 10-bit ADC . target version is 40 MHz (data conversion at 32 MHz) - ADC Driver has changed from slide 11 . Texas: THS 4141 (5V chip) . could not properly simulate Analog Devices AD8138 . see schematics for more details (see page 32) > L1Cal Home --> Saclay --> ADF --> Full Schematics . anti-aliasing low-pass filter > cutoff freq. = 15MHz > On the anti-aliasing filter, only the capacitors in the feedback loop of the ADC drivers are soldered (surface mount component). The others capacitors are through hole types and the exact value can be determined during tests. - Driver output to ADC - DACs for pedestal adjustment (schematics p.48-49) . Octal 10-bit DAC . ref voltage from ADC buffered using op-amps . DAC output subtracted from input at level of ADC driver . note: this subtraction could also be done digitally . advantages of doing it in analog > a) faster > b) subtraction done closer to source of signals o Schematics Description - L1Cal Home --> Saclay --> ADF --> Full Schematics - p.1: VME rows A,B,C - p.2: VME row Z-D (reserved pins shown) - p.3: J2 rows A,B,C . rows A,C: analog inputs - p.4: VME J2 rows Z,D (most grounded) - p.5: J0 pinout . TAB output . SCL timing input (only to one ADF per crate) > SCLIF_CABLE_REM_B, SCLFIF_CABLE_LOC_B: detects whether timing cable is attached - p.6: buffers for VME interface - p.7 VME prom - p.8: CPLD - p.9: debug connector - p10-14: FPGAs - p15...: capacitors and coupling - p.24: channel-link serializers - p.27: PLLs. latch, etc - p.28: front panel led, jtag - p.29: LVDS termination - p.30: debug connector - p.31: DC-DC converters 3.3V, 1.5V - p.32...: analog channels - p.48-49: Zero adjust serial DACs o ADF Layout - layout uses Cadence as tool . routing via Allegro (part of Cadence) - 14-layer, class-6 board . 1.8 mm thick (>1.6mm VME standard - but fits in crate) . 2 ground planes (some signals in one of these) . 2 power planes . some controlled impedance traces - Top of Board: FPGAs, VME, half of ADCs - Bottom: other half of ADCs, capacitors - FPGA = BGA w/ 1mm pitch o Timing of System - Clock from SCL via SCL timing card --> one ADF . all cables to ADF crates are equal lengths - this ADF fans out signals over J1 reserved pins to other ADFs . only difference in signal timing from propagation delay on backplane . plug SCL receiver into middle card in crate o ADF Digital Section (slide 12) - input logic selects: . ADC data . history buffer data (pre-loaded test data) - ADC input also --> Magnitude Comparitor ==> self-trigger . intended to record pulse-shapes for FIR coeff calculation (calibration) - Decimator (slide 13) . ADC runs at 4x132ns (BCx4) . FIR output at BCx2 . Logic at BCx8 > (multiplications are done at BCx16) . throw out 1-of-2 samples (selectable on per channel) > allows to adjust the phase of sampling clock to 16ns > no delay-line circuitry > finer tuning by adjusting coeff's of digital filter - Convolver = Digital Filter (slide 15) . coeff's = 6-bit, samples = 10-bit, 8 tap . coeff's programmable at run time over VME - Peak Detector (3-point) . outputs 0 if no peak found - LUT for conversion to Et (8-bit) (slide 18) . implemented as FPGA block RAM (2k x 9-bit, only 8-bits used) . can set pedestal here . detects arithmetic overflow . The 10 lower address bits are driven by 10 bits of the peak detector selected among 16 bits output (one can select the 10 MSB's or drop 1, 2 or 3 bits using the circuitry on slide 17). The bits that are dropped are OR'ed together and drive the MSB address of the Et LUT. - Outputs to serializer . 8-bit Et . random number . constant value . raw data inside history buffer (following L1A) > this is 8-bit (rather than 10 in slide) o Peak Detector & Decimator (slide 16) - decimate by x2 - can turn off peak detector o Latency Adjust - all logic clocked at BCx8 - 32-bit Shift Reg used to adjust latency . fine: BCx1/8BC - BCx7/8 all channels the same . coarse: BCx0 - BCx3 channel-by-channel o Random Generator (for TAB test) (slide 20) o History Buffer (slide 21-23) - 1) Test Mode: pre-load memory & play at input of dig.filt - 2) Normal Mode: contains history of past 32 BC's . triggered by L1Accept or other triggers . raw data . convolver output . final results . can freeze this and read back or send to TAB (raw data) - The history buffer is a 1024 x 18 bit block RAM written at BCx8. It contains 128 BC's of history. Each BC data takes 8 18 bit words: . the output of the convolver (16 MSBs) is written 4 times (only 2 different values are produced per BC); . the 4 other words are composed by the ADC raw sample (10 bit) concatenated with the output of the Et LUT (8 bit). As the ADC runs at BCx4, all raw samples get recorded. Because the output of the Et LUT changes only once per BC, the same output is recorded 4 times in the history buffer. Convolver output words and ADC raw data + Et words are interleaved in the history buffer. o BX to TAB (slide 24-25) - counter in each FPGA: 1-159 . only FPGA-0 counter sent out . no checks on whether sync'ed or not at ADF level - preset to 1 by BX-marker from SCL - sent out to TAB on normal events - on L1Accept send . BX number (8-bit) & TURN number (16-bit) . note: only 8-bit frames are sent . can also be read out from each FPGA over VME o Parity Calculation (slide 26) - can do parity over all data bits or a sub-set o Data Transmission (slide 27) - Frame signal sent on LSB - LSB of data sent first o 8/10 bit frames (slide 28) - only 8-bit frames are now required o Triggers for the ADF system (slide 32-33) 1) L1Accept generated by TFW (via SCL) 2) L1Accept w/ Monitoring - monitoring signal generated by TCC (asynchronously) - L1 Qualifier bit used to indicate which L1Accept should be used for collection of monitoring 3) L1 Software Accept - generated async. by TCC - issued by one ADF card - bounced to all cards by SCL Interface 4) L1 Self Trigger - wire-ORed for all channels and all ADF cards - sent back to all ADF cards by SCLIF o SCL Signal Fan Out (slide 36-40) - SCL Interface Fan Out Card (SCLIF) . cable to each ADF crate --> one ADF in each crate - SCLIF cable pinout (slide 38) . sends 8-bit serial stream of data . Downstream (SCL-->ADF) & Upstream (ADF-->SCL) command streams - Error pin used to send ADF error to SCLIF . individ. ADF errors send on reserved J1 pin o Clock Fanout (slide 41-43) - talk is not up-to-date - now using external PLL to get BCx4 - 64 MHZ oscillator on ADF card (divided by 8) used for local clock when SCL is not there - phase alignment (slide 43) . all clocks on all FPGAs in system are aligned o Status of Design - schematic on web is not latest version . number of capacitors has changed (rest is ok) - firmware and software are available (ask Hal for files) . VHDL simulation using any VHDL simulator . can be interfaced to ModelSim simulator to interface to hardware . Leonardo used for compilation o Status of ADF Prototype - a few minor resistor & led errors - DC-DC converters appear to work - have cabled one card - VME interface is working - downloaded CPLD firmware through Jtag - read/write data to CPLD - haven't yet downloaded firmware to FPGAs (through VME) - FPGA firmware download using Jtag seems to work . but FPGA logic seems to have problems - work will resume on this on Aug. 17 - bring ADF to Fermilab Oct. 10