RUN 2B L1CAL MEETING MINUTES
			     21 August, 2003

Present
o Columbia:	H.Evans, J.Mitrevski
o Fermilab:     G.Cancelo, V.Pavlicek, S.Rapisarda
o Maryland:	D.Baden
o MSU:		M.Abolins, D.Edmunds
o Northeastern: D.Wood
o Saclay:       D.Calvet
o Virginia:	B.Hirosky



Fermilab Status: Stefano & Gustavo
----------------

o Test Waveform Generator System
  - Hardware Status: 2 channel test system
    . Xilinx Test Card:
      > Jtag and RS232 inputs (from PC) implemented
      > currently uses Excel spreadsheet for input
      > work being done to improve the interface
    . AD9765 Card (Digital to Analog Conversion) & Amplifier
      > basically working - but still some work to do
    . Filter Prototype back from manufacturer
      > should be ready by next meeting
      > signal is clean enough that this is probably not necessary
  - Still working on the spec for the Final System


Saclay Status: Denis Calvet
--------------

o Received Cable for Cable Harness this morning
  - missing connectors shipped on Monday
  - all components by middle of next week
  - still need to know how long from splitter to Test Area
    . will cut 16 cables and assemble prototype after this

o SCL Interface to ADF Cables
  - same as ADF-to-TAB
  - have received 6 of these cables (after 6 month delay)

o SCL Mezzanine Card
  - layout finished
  - pcb fabricated and (probably) received
  - will check whether it has been stuffed

o Splitter
  - 2nd layout should be done by end of Aug
    > add forgotten heat sink, DC-to-DC converter, etc.
  - make 3 more splitters after this

o Channel Link Receiver Mezz. Card
  - plugged on FPGA eval kit - used as tester
  - layout finished - few things left to correct

o Reduced ADF
  - 1 channel
  - plugs on FPGA eval kit
  - layout in progress

o ADF Prototype
  - power: ok
  - few minor errors found: led's, resistors
  - configured serial prom for bridge, cpld for programming interface
  - VME interface working
  - downloading firmware for FPGAs
    . previously could not do this
    . found the problem yesterday
    . now can download via Jtag & VME interface
  - simple FPGA test firmware working on only 2 of 4 chips
    . 2 of the FPGAs generate huge noise on ground and power planes
      > note: one of the non-working ones is in charge of clock
        distribution
    . still investigating the problem
    . has to be solved to continue debugging the board
      > could try to work with only 2 FPGAs - but would not be an
        optimal way of doing things
  - analog part
    . not yet begun to test this
    . note: clock for ADC generated by FPGA
  - discussion
    . the FPGAs do not draw excessive currents
    . they are BGAs: manufacturer has x-rayed them --> ok
      > but this is not always a good test
    . Fermilab has a BGA rework facility
      > but this would be rather time consuming 
    . currently checking I/O pins
    . have a 2nd ADF pcb with enough components to stuff it
      > can stuff this if find that problem is with assembly
      > would take 2-3 weeks
    . isolate analog part from clock distrib?
      > analog gets its power from backplane
      > FPGA power from DC-DC converters
      > should not have coupling
    . remove DC-DC converter & power externally?
      > not easy b/c soldered onto board - need to compensate for
        impedance - but this is a possibility



Columbia Status: Hal Evans
----------------

o TAB prototype testing continues
  - systematically going through all inter-chip connections
  - no hardware problems found yet


Results of the First Integration Test: Jovan Mitrevski
--------------------------------------

o Phase-1 Test on July 30-31 at Fermilab
  - VME/SCL-to-SCL Hub Test ==> success!

o Infrastructure Installed in L1Cal Test Area
  - 9U VME crate (VME/SCL)
    . Bit-3 & VME/SCL installed
  - 6U crate (ADF) installed
  - PCs for control: linux and windows

o Tests (all ok)
  - locked onto SCL clock (CLK7)
  - received data from SCL
    . recognized SCL init & turn: used this to start TAB
  - checked BX number from SCL
  - L1Period & L1Accept

o VME/SCL & Bit-3 shipped back to Nevis


New TAB/GAB Test Card: Hal Evans
----------------------

o Building a TAB/GAB Test Card at Nevis
  - used to test LVDS links in TAB/GAB system
  - ADF-to-TAB: Channel Link   424 MHz
  - TAB-to-GAB: Stratix	       636 MHz
  - details available in talked linked off agenda

o Cost & Schedule
  - Cost		~$2000
  - Board in Hand	~12-Sep
  - should not delay layout of prototype GAB by very much
    > still aiming for mid-October to have GAB in hand