RUN 2B L1CAL MEETING MINUTES 4 September, 2003 Present o Fermilab: G.Cancelo, J.Kotcher, V.Pavlicek, H.Weerts o MSU: M.Abolins, D.Edmunds o Nevis: H.Evans, J.Mitrevski o Northeastern: D.Wood, E.Barberis o Notre Dame: A.Goussiou o Saclay: J.Bistricky, D.Calvet, E.Perez o Rice: P.Padley Fermilab Status: Vince Pavlicek ---------------- o Most of the group is off on vacation (mandated by director) o Work continues on user interface - more next week Saclay Status: Denis Calvet -------------- o ADF Tests - Document describing testing posted on the web . http://www-clued0.fnal.gov/~perez/R2BTRIGGER/ADF_Description/Tests.html - VME interface, local bus, clocks working - Current Issue . PLL for x2 clock multiplication still not working . drop for the time being while concentrate on analog - Analog Part . started work 3 days ago . BLS input 0 - 6 V differential . translated to 0 - 2 V differential at ADC input w/ 1.25V level shift . problems with oscillation for inputs >3V . tuning capacitors to help out with this - ADC . tested 2 channels . converts correctly - output ok - Digital Part . not yet tested connection of FPGAs to Channel Links . probably can't really test this until have the TAB . also need PLL logic o Splitter - modification finished - will start new production after this is checked o Mezzanine Test Cards - 1-Channel ADF - needed to understand analog section . much easier to do on this card than the full ADF - Channel Link Receiver o SCL Card - have received this card - under test - should be ready for Integration o Cable Harness - half of one cable harness assembled - made this 2.5 m long after discussion w/ Dan - some problems w/ mechanics of crate . need to do more surgery o Integration - probably during/directly after Oct. Trigger Workshop - Denis will arrive a few days before the meeting . will stay ~2 weeks - Emmanuelle will also be there - need to find a 6U PCI-VME interface - Software Licenses . Xilinx place-route license definitely needed . simulator not absolutely necessary . Leonardo Synthesizer: only needed for full ADF firmware o Problems programming FPGAs 0,2 mentioned last week - noise turned out to be due to logic analyzer . logic analyzer was only connected to FPGAs 0,2 - remaining problem w/ FPGA 0 . simple design that connects to clock doesn't work . but more complicated designs seem to work fine Columbia Status: Hal Evans ---------------- o TAB prototype testing continues - "Chip 10" (global chip on TAB) verified . inputs from Sliding Windows chips . output data to GAB . output to Cal-Track match o GAB - layout of the GAB is essentially done . a few lines and test points remain to be added - working on simple trigger term firmware . note VME and LVDS receiver firmware already done - after data transmission tests (see below) will start independent checking of the GAB layout o TAB/GAB Test Card - layout finished - board sent out for quotes (27-Aug) - board submitted to fabricator Tues. (2-Sep) . will drive the board to the assembler (for Stratix mounting) as soon as it comes back from fab. - Tests to do when board comes back . channel link input to TAB . test 680 MHz TAB-GAB data transmission using Stratix LVDS transmitters and receivers on test board > same configuration as in final TAB-GAB system General Remarks: ---------------- o Witherell's decision on the Run IIb Silicon upgrades posted off of Documents page - http://www.nevis.columbia.edu/~evans/l1cal/docs/docs.html o Silicon upgrades cancelled - Non-Silicon upgrades continuew - note that non-silicon upgrades were labeled "Essential to the reach the scientific goals of the luminosity upgrades" - this puts us in class 2 (of three Run IIb priority classes) . 1) Must be done: accel & detector operations, computing . 2) Essential: lumi upgrades, accel personnel, non-Si, Neutrinos . 3) Important: Si, accel infrastruct, reserve o Important to continue focus on L1Cal despite the lab's stance - actively attempting to strengthen L1Cal group ***** if you have concerns, let us know ***** o We need to produce a "Case for the Run IIb L1Cal without Silicon" - send ideas to Hal and Maris - Three Main Areas a) operation of the experiment at high inst. Lumi b) exciting physics without the Si upgrade c) minimizing the experimental downtime due to the upgrade - try to present this at the Trigger Workshop in October o Discussion - even in Baseline lumi profile, back of envelop calc's say lumi gets high enough that trigger upgrade is necessary - note: L1 bandwidth that we can ultimately achieve is probably ~2.5-3 kHz . puts extra demands on L1 trigger - need to make physics case for detector w/out Si upgrade - Schedule - if trigger is ready early, can we put it in? . would need to be coordinated with accelerator shutdown . but much more latitude . need to look into this . but constraint is to minimize experimental downtime - Collaboration Issues . need to get explicit support from collaboration for project to continue . "Case for Trigger Upgrade" document will help here