RUN 2B L1CAL MEETING MINUTES 18 September, 2003 Present o Fermilab: D.Edmunds, V.Pavlicek, S.Rapisarda, H.Weerts o MSU: P.Laurens o Nevis: H.Evans, J.Mitrevski, J.Parsons o Northeastern: D.Wood o Saclay: J.Bistricky, D.Calvet o Rice: P.Padley Fermilab Status: Stefano & Vince ---------------- o Analog part - not getting enough gain from a single amplifier - board has room for 2 amp's, will add another later this week o The TWG will be needed when ADF arrives at Fermilab - see Integration MSU Status: ----------- o Learning linux environment on new PC Software Discussion ------------------- o Saclay Test Software for multiple cards is available - source code sent to Hal 2 months ago - standalone running + interface with VHDL simulator - can also run with PCI + reduced ADF card - real ADF running using Bit3 . mod's to run with Vertical interconnect and Single Board Computer - Code based on ASCII code interpreter . mult. clients over TCP/IP socket for issuing commands/receiving replies - plan is to stop software development here o What Saclay expects - software to talk with ADF TCP/IP socket - provide commands to ADF system: . LUTs, filter coeff's . read status, etc. o Options - a) leave TCP/IP socket framework - b) extract actual control code and port to control computer - will need to determine exactly how this will evolve o Offline Software - determine filter coeff's, etc. . Saclay will not lead this effort . Examine and DAQ framework not well suited for acquiring the data that will be necessary to determine these coeff's - note: a first pass of the firmware for digital filtering already exists and is quite flexible Saclay Status: Denis Calvet -------------- o ADF Tests - Document describing testing posted on the web . http://www-clued0.fnal.gov/~perez/R2BTRIGGER/ADF_Description/Tests.html o Analog Channel Measurements - see slides linked off of agenda - measured two things . 1) noise when nothing connected to analog input . 2) noise when pulse with shape similar to trigger pickoff - results (no bandwidth limiting cap on input) . channels 0-7: noise ~ 1-2 lsbs . channels 8-15: several channels quite noisy . channels 16-31: most channels quite noisy - when filtering cap added to channel 28 . --> noise improved slightly - results w/ 2.5 V input pulse (1/2 of full scale) . channels 0-7: behave quite well . channels 8-23: some noise > channel 14 has cabling defect on board --> 1/2 expected ampl . channel 24-31: significant noise - checked whether source of noise is logic analyzer . eliminated logic analyzer as noise source - observations . channels close to connector are least noisy - playing with filtering cap on channel 30 . can decrease noise to reasonable amount if choose cut-off freq. sufficiently low - probably need to make layout mod's to help out this noise situation ==> will go through 2nd iteration on ADF prototype . this could be quite quick, if only filtering changed . much longer if more substantial mod's to be made . Dan will talk with Denis about this o ADC Driver & Pedestal DAC - had oscillations when going to full ampl at input (6V) . these are due to limits on output swing of driver in conjunction w/ common mode voltage on ADC driver . currently would be limited to -1V - +1V swing: not enough . note: this effect was not modeled by SPICE - common mode voltage (1.25) not optimum . this is hard-wired on the board ==> need to make a modification to PCB (layout changes) o Serial DAC (used for pedestal correction) - b/c common mode voltage is not in acceptable range - cannot set DAC properly - need to retune resistor values . will do this on 1-channel test card o Other analog issues - all other signals: clocks, etc. seem to be working fine o Digital Part - BC clock generation . use PLL for 4xBC - OK . use on-board PLLs in FPGAs for 8xBC - NOT OK previously > problem is probably with reset logic > seems to have been solved - but needs to be confirmed - will also check LVDS outputs on scope o SCL Interface Card - get SCL_sync error when plug mezzanine card in . not surprising since no input to mezzanine - Dan will talk with Denis about getting a special mezzanine to do these tests o Splitter - 2nd layout finished - will produce 3 more splitters - should take about 5 weeks Columbia Status: Hal Evans ---------------- o TAB prototype internal testing basically complete - All internal connections on the board verified . except ICR data sharing - firmware being written now - External connections . VME (via VME/SCL): > fully tested . SCL (via VME/SCL) > tested w/ simulated SCL signals & with real signals at Fermilab . ADF (channel link) input > will use TAB-GAB tester for 1st try . GAB LVDS output > output format verified > will use TAB-GAB tester . Cal-Track > format tested > need to go to Fermilab to test actual transmission . L2 Output > proposed format verified > need to go to Fermilab to test actual transmission > how difficult would this test be? o GAB - layout of the GAB is done . will verify layout as soon as transmission mechanism tested using TAB-GAB test card o TAB/GAB Test Card - board received back from fabricator on Mon. 9/15 - sent out for assembly - should be back next week - control software being written Integration Test: ----------------- o Emmanuelle and Denis have booked flights to Fermilab - Oct 7-17 o Dan will be at Fermilab for 1st week, Philippe for the 2nd o Main Goals 1) SCL signals to ADF 2) ADF to TAB signal transmission o Saclay Needs - will ship a PC --> Fermilab . will try to set this all up (except for license) before shipping . where to ship it? . need a monitor for the PC - will need digital scope (~500MHz, 2Gsamples, 4 channels) - also a logic analyzer (200MHz, 64 channel) - do we need to ship PCI-VME interface? . would be useful to keep the Saclay one at Saclay . Dan will look into getting one at Fermilab . Darien had checked a few months ago with Marvin, who didn't have the right model available for long-term loan - need Xilinx place-route-synthesize license . synthesizer = Leonardo for full firmware . test firmware = included in Xilinx software . do not have key - will need access to license server - Dan will get Denis in touch with John Anderson about . PC, scope, logic analyzer - 6U crate will be set up/tested for power . Dan will check this o Nevis Needs - have 2 PCs: linux and windows - Windows PC has Altera software . used only for firmware changes - crate: have borrowed one from Fermilab . still in Test Area - boards . VME/SCL, TAB, TAB-GAB test card, Bit3 - ADF-to-TAB cables o Scheduling - timing will be very tight for these tests . need to coordinate with the schedule of Trigger Workshop - Saclay & Nevis should produce task lists to clarify exactly what work needs to be done and when it can be scheduled