RUN 2B L1CAL MEETING MINUTES 2 October, 2003 Present o Fermilab: D.Edmunds, V.Pavlicek, S.Rapisarda o MSU: M.Abolins, C.Brock, P.Laurens o Nevis: H.Evans, J.Mitrevski o Northeastern: D.Wood o Saclay: J.Bystricky, D.Calvet, E.Perez o Rice: P.Padley Fermilab Status: ---------------- o No major changes - mainly packaging the 2-channel system o Hardware Status - 1 Xilinx FPGA test card - 1 AD9765 Test Card (Digital to Analog) - 2 AD8138 Cards (Amplifier/Filtering) o Software - platform runs on Windows o Everything should be ready for ADF tests at Fermilab MSU Status: ----------- o Communications Architecture - L1 Cal TCC talks to "Control Crate" . may rather use a dedicated PC to run ADF system (current design) . this PC would communicate with L1Cal TCC via TCP/IP . would be an advantage during commissioning . in the final system a common PC would probably be best - Control Crate . 1 Bit3 > sharing Bit3 interface b/w TABs & ADFs may be difficult b/c ADFs take all of address space > also ADF software not set up for concurrent access > note: could have multiple Bit3 cards in crate > concurrent access problems can also be overcome > Note from Denis added after the meeting I have checked that, and in fact each ADF card takes 256 KB of address space + a few more (one 4 KB page will do). So in total, the ADF system needs ~21 MB and a Bit3 interface can map 32 MB at a time. Also, it is easy in my software to acquire/release the spin lock of the Bit3 interface driver for each bulk of transactions, so that concurrent access from several applications can be made. What I need however is a VME interconnect with 4 slaves attached to it and one 6U slot to plug the SCL fanout card (this card will not have a VME interface and does not need slow control). So we could certainly have a single control crate with 1 bit3 interface, 2 VME interconnect masters and the SCL interface for the ADFs plugged in 6U slots, and the VME/SCL interface for the TABs plugged in a 9U slot. We can discuss that in more details next week. . 2 Vertical Interconnect Master --> ADF crates . 1 VME/SCL --> TAB/GAB Crate . 1 ADF SCL Interface Card (6U board - needs adapter) - 4 ADF crates - 1 TAB/GAB crate - Readout Crate . 1 VIN . 10 VRBs (signals from TAB/GAB split to L2 also) . 1 SBC - discussions on this will continue when everyone is at Fermilab o L1Cal TCC Functionality 1) Control - Configure (download firmware) . once after power-up - Initialize . set to known state - test that everything is ready - Program (run time) . parameter download fro particular trigger list 2) Monitoring 3) Tests/Diagnostics - Communication Tests - Board-Level Tests - Global System Tests - Calibration 4) Questions - How is firmware loaded in TAB/ADF . ADF: downloaded via VME . TAB/GAB: downloaded via VME - Initialize . what is required here for ADF/TAB/GAB - VRB setup - Run-Time Programming . ADF: exclude channels, filter coeff's . TAB/GAB: thresholds - COOR will want to control this - Monitoring . ADF: need to freeze history buffers periodically Saclay & Nevis will make current code available to Philippe Saclay Status: -------------- o Cable Harness - assembly complete - all 32 cables tested - shiiped to Fermilab o PC for ADF control - software installed - shipped & received at Fermilab - Xilinx license: license on PC should work at Fermilab - Firmware reworked to use Xilinx default synthesizer . rather than Leonardo . solves Leonardo license problem - VHDL simulator - ModelSim . not available at Fermilab . will not be able to do a VHDL simulation while at Fermilab . probably not an issue o SCL Interface and ADF Cards - paperwork done for these complete o Bit3 - have found one to borrow at Fermilab o SCL Interface - testing mainly complete . only a few minor problems found o ADF Tests - Clock Generation in Xilinx chips . clock distribution/generation on board changed . previously > external PLL --> BCx2 > internal PLL --> BCx8 (from BCx2) . now > onboard clock --> BCx2 (standalone mode) SCL Interface sends BCx2 (SCL mode) rather than BC > external PLL --> BCx8 > Xilinx internal DLLs not used . Xilinx DLL issues (from Xilinx web page) > very sensitive to power supply noise: ADF may not respect this - Test SCL Distribution to ADF connection . BC clock distribution scheme seems to work (for local oscillator) > need to test this further . Problem with clock jitter with DCNs on SCL Distrib card > BCx2 signal generated from SCL clock not stable > probably same problem as above > no solution yet - may need to use local oscillator for integration - Plan . stop tests this evening to prepare for move to Fermilab o Splitter - in production for 3 additional cards - should be there in Oct. Columbia Status: ---------------- o TAB/GAB Test Card - card arrived at Nevis - testing going well . communication with card established . working on TAB input data timing: should be sorted out today - will test all TAB input channels using this card Integration Test: ----------------- o no further discussion: ~everything seems ready Any Other Business: ------------------- o Run IIb Trigger Workshop (Oct 11-12 at Fermilab) - L1Cal Sessions on Oct 11 (Sat.) morning - Proposed Goals: 1) discussion of issues we have not talked about lately . digital filtering . controls and monitoring . physics studies of the trigger 2) attract/introduce new groups to project - Talks . one overview talk (Hal) . mainly PR - Discussion . this should be the meat of our part of the workshop . please send suggestions for topics to Maris, Hal, Darien and Paul o Re-baselining - need to have proposals from each group *well before* Oct. 14 deadline for presentation to Lab - this will be basically our only chance to make changes - so we shouldn't lose it