RUN 2B L1CAL MEETING MINUTES
			     16 October, 2003

Present
o Fermilab:     D.Calvet, G.Cancelo, P.Laurens, J.Mitrevski, 
		V.Pavlicek, E.Perez, V.O'Dell, S.Rapisarda
o MSU:		M.Abolins
o Nevis:	H.Evans
o Rice:         P.Padley


Integration Tests:
------------------

o Integration Test has been a huge success so far!
  - thanks to Denis, Emmanuelle, Dan, Philippe, Jovan and John

o Goals Acccomplished
  1) ADF gets timing from SCL via ADF Timing Test Card
  2) TAB gets timing from SCL via VME/SCL card
  3) Data transfered from ADF to TAB
     . works both with ADC's on and off
     . only ~32 events at a time read out and verified
     . no sync between start of ADF data and start of TAB
       > requires SCL Init to be seen at ADF
     . temporary connection of cable to TAB is tricky
       > will be improved with full TAB backplane
  4) TAB to Cal-Track (actually L1Muon) data transfer
     . note: this was not in the original plan - but things were going
       so well that we tried it anyway
     . timing of sync-gap signals checked on scope
       > this has historically been the hard part
     . no mechanism to dump data at L1Muon end, but...
     . have sent known patterns (1 e per 32 events, 2 e per 32 events,
       etc.) and seen consistent changes in L1Muon trigger rates
       > also have checked that these triggers occur in correct timing
         bin 
  5) TWG data transfered to ADF
     . see below
  6) Large volumes of data between ADF and TAB
     . check for errors using parity
     . goal is to produce estimate of bit error rate
     . firmware to calculate parity debugged
     . no parity errors observed on serializers 1 and 2
       > constant data pattern
       > run for ~1 minute
     . some errors on serializer 3
       > may be some noise on this

o Still on the List
  1) Continue large data volume tests
  2) TAB to L2 data transfer
     . note: note in original plan
     . if this can be verified then TAB is ready for production
       > after TAB-to-GAB data transfer tests at Nevis using
         TAB-to-GAB test card
     . will talk with Reinhardt about this
  3) Test that can receive L1Accept, SCL Init on ADF Timing card


Test Waveform Generator:
------------------------

o October 15 Tests with ADF
  - TWG, computer, scope brought to Test Area
  - sent sequence of short pulses to ADF

o ADF Results
  - input signal 2V P-to-P
  - use cable harness for input of signals
    . 1st test of this with "real" signals
    . note two of the cables were broken
  - Channels 0-15
    . ~7 working well, rest have some noise
  - Channels 16-31
    . more noise observed
  - consistent with measurements at Saclay
  - change amplitude of TWG input
    . 0V --> no change in baseline
    . 1V --> slight shift down in baseline
    . higher --> baseline continues to shift down
    . this is normal b/c of DC-balance on input to ADF
  - discussions w/ Dean Schamberger started to understand how this
    will work with real signals
    . important b/c baseline shifts --> inaccuracies in E-measurement

o Plan
  - will make SPICE simulation back at Saclay about this
  - Dean will make measurements of DC component of BLS signal


News from the Re-Baselining:
----------------------------

o Focus has been on Silicon
  - should hear "by the weekend" 

o New Trigger Costs presented (additional ~ $500K)
  - no real problems with this so far
  - people very impressed by technical progress