RUN 2B L1CAL MEETING MINUTES
                13 November, 2003

Present
o Fermilab: D.Edmunds, S.Rapisarda, H.Weerts,
o MSU:      M.Abolins, P.Laurens
o Nevis:    J.Mitrevski
o Saclay:   J.Bystricky, D.Calvet


ADF Status (D.Calvet)
----------

o ADF prototype board now back at Saclay.
    - Continue testing

o Clock Multiplier
   - On FPGA clock multiplier (x2) still not working
   - Xilinx has been contacted, no solution
   - Look for an alternate path
   - Upgrade the on-board multiplier from x4 to x8
   - Make a small (~1 cm**2) transition board to accommodate
     a different multiplier chip with different pinout.

o Simulated Raw Data Pattern
   - Preload raw data pattern for input to digital filter
   - Fix small firmware bugs
   - Tests successful

o Circuit board received for single ADF Channel test
   - Now being assembled
   - Plugs into Xilinx evaluation kit
   - For study and tuning of parameters (capacitors, resistors, etc)

o Circuit board received for Channel Link receiver
   - Now being assembled
   - Plugs into Xilinx evaluation kit
   - For testing ADF->TAB communication

o Produced a SCL Fanout Card document
   - Describing the functionality and interfaces needed by ADF system
   - This card will not be produced by Saclay
   - Document meant for UIC who expressed interest in building this card
   - Document will be on the Saclay web pages shortly

o In contact with D.Edmunds via EMail
   - Plan for optimal transfer of knowledge
   - Plan for optimal timing of Dan coming to Saclay
   - MSU can practice with the VHDL model and software
   - Saclay can continue testing Analog and Channel Link
   - Saclay could send ADF card back to FNAL around Christmas
   - ADF card could then stay at FNAL for a few months
   - MSU could do analog tests at FNAL with beam signals
   - E.Perez will be at FNAL during the first 2 weeks of December
     but this will be before Denis is ready to part with the card


MSU Status
----------

o ADF Tests at FNAL (D.Edmunds)
   - Support the idea of testing ADF card at FNAL with beam
   - Gain practical experience operating the card
   - Would propose to also do endurance test of link to TAB
   - FNAL has no Christmas shutdown currently planned

o How to proceed (D.Edmunds)
   - MSU can use Cadence viewer to study layout files
   - Practice with the VHDL simulation
   - Investigate whether MSU should stay with UNIX based Modsim tools,
     or switch to PC based xilinx tools

o Trip to Saclay (D.Edmunds)
   - Should coincide with layout of Revision 2 of ADF board
   - Should start picking a week soon, probably February 2004

o Online Software (P.Laurens)
   - Continue preparation work
   - Learning DZero environment
   - Learning Linux
   - Start evaluating using Tkinter for a user interface.



Test Waveform Generator Status (S.Rapisarda)
------------------------------

o Prototype
   - Memory READ/WRITE and RS232 channel tests
   - Added a 2nd amplification stage to increase differential voltage
swing
     and provide a common mode voltage or 0V

o In Progress
   - Filtering to limit bandwidth of output signals
   - SCL interface to provide synchronization
   - Improvements of the system clock
   - Writing documentation

o TWG System
   - Working on Specification proposal. Comments and ideas are very
welcome.

cf. http://www-ese.fnal.gov/D0Cal_TWG/Report_Nov13_2003.pdf



TAB/GAB Status (J.Mitrevski)
--------------

o TAB->GAB communication
   - Initial concerns with temperature dependance of noise margins
     seem to be solved

o Now ready to do final check of design and fabricate GAB

o Progress with TAB raw data path
   - Getting closer to start assembling more TABs

o Nevis will investigate the possibility of bringing a TAB back to FNAL
   - For 2nd round of endurance tests of ADF->TAB link
   - Likely time scale would be January 2004
     after analog tests and before layout of ADF V2

o Jovan is moving to Chicago around the Christmas Holiday