RUN 2B L1CAL MEETING MINUTES 11 December, 2003 Present o Fermilab: D.Edmunds, S.Rapisarda, A.Stone o MSU: P.Laurens o Nevis: H.Evans, J.Mitrevski o Northeastern: D.Wood o Saclay: J.Bystricky, D.Calvet Test Waveform Generator Status (S.Rapisarda) ------------------------------ o Software: no changes o Hardware - SCL Interface added ==> ability to get system synch - passive adapter connects SCLR to TWG Xilinx card o Work In Progress - modifying Xilinx firmware to use SCL timing info - implementation of filtering - speed up system clock - updating documentation (see web page) - should be ready be early Jan. o Please contact Stefano w/ comments about system - board will be finalized very soon - questions . what will be trigger on . fanout capabilities . etc... TAB/GAB Status (H.Evans) -------------- o GAB sent to fabricator on Dec. 2 - quote received Dec. 4 - (quote for assembly also received) - waiting for purchase order from Columbia purchasing . expected beginning Jan. ADF Status (D.Calvet) ---------- o 2nd version of Splitter submitted to Fab. in September - company has lost components - now found - delay in delivery: should have been available 2-3 ago . new schedule: mid-Jan . can be at Fermilab by end-Jan o ADF Clock multiplication - now working within Xilinx . problem was in the way clock was driven on backplane (wrong characteristics) - will not need to make foreseen modifications to get around this o Serial Communication b/w ADF and SClF - almost completely tested - will need to retune delay lines for this at Fermilab - note: this link is necessary to transfer L1Accept, Triggers, Control, etc. between ADF and SCLF . w/out it can only transfer clock o ADF Tests - Preloaded Data in ADF Memory: working fine - using this to check various aspects of the digital filter/peak detector - have verified that ADF produces same output as test software with input signals based on Dan's measured signals - final LUTs tested - synchronization of all channels checked - synchronous commands to ADF tested . software triggers, etc. . can do this to one crate only and via SCLF mirroring to all crates - Self Triggering Mode . comparators on all channels ORed over ADF ==> self trigger - Tested that can send raw data to TAB based on L1Accept . sends 8 MSBs of 10-bit input data - have not tested BC count, etc. since no access to SCL o New Boards Received: Channel Link Tester - plugs into Virtex-II evaluation kit - will use to make tests of jitter rates - using same type of pseudo-random generator as on ADF - board being debugged - Emmannuelle will work on software for this o New Board 2: Single Channel ADF - allows resistor/capacitor values to be tuned - analog part checked - will check digital part soon - hope to be able to find way to set correct ref voltage for ADC . note: this won't solve ADF noise problem o SCLD Board - document finished - sent to UIC - vhdl code rearranged and sent to UIC o Shipping ADF boards to Fermilab - Denis can ship ADF and reduced SCLD/Virtex Eval kit next week - But not all planned measurements of ADF are complete . if can solve ADC ref voltage problem, then will cable a 2nd ADF for continued tests at Saclay - Dan could start work on the ADF at Fermilab in January . would like at least a week with ADF before TAB arrives to learn how to operate it MSU: Online Software (P.Laurens) -------------------- o Online Software for Integration - integration test will be based on existing ADF software o Porting online software to Linux - work is continuing here in moving old Windows Monitoring software to Linux . this could serve as a basis for Run IIb monitoring code - could finish this quite soon o Next Step - how to integrate existing ADF and TAB/GAB software into online system . should start in Jan. UIC: Cabling Issues (A.Stone) ------------------- o Alan is discussing this with Dan - will produce a draft cabling plan soon - Alan will give a presentation at the next meeting SCL Fanout Card for ADF ----------------------- o Agree on name for this card: SCLD (SCL Distributor) - note: this is referred to as the SCL Fanout in the vhdl code o SCLD Document available on web o Jovan has prepared a talk on the VME/SCL used for the TAB/GAB - this is linked off the agenda and the Hardware page Integration Test Discussion --------------------------- o ADF Tests that could still be done at Saclay - ADF board "as is" should be useful for integration . may have to cut a few traces to get correct ref. V on ADCs - solving noise problems probably requires re-lay-out - pedestal problem: not something that should affect integration - jitter rate measurements will take some time to do - preference: ship board next week before Saclay holiday shutdown . use 2nd board (to be stuffed soon) to continue measurements at Saclay . this can also be used to do multiple-ADF tests o To do for Tests - Power Supplies . for TAB need: 48V & 6V supplies - Cables . spares for ADF-to-TAB . cables from splitter already installed - Longer Term . set up L2/L3 readout rack o Goals - ADF Tests that couldn't be done last time . Digital Filter operation using synchronized clock > could be a good use of TWG w/ SCL clock > measure latency, correct phase alignment . Measure ADF --> TAB communication error rate - Data from splitters --> ADF --> TAB . note: additional splitters will come later - TAB --> L2/L3 . output fiber from test stand --> unused input on existing L1Cal VRB . capture data in crate and dump to file . requires that sending of data is in response to real L1Accept - MSU people should learn how to use ADF card o Schedule - aim for test as soon as possible - probably mid-late Jan.