Minutes of 22-Jan-2004 Run IIB L1Cal Meeting Attending: 1. Fermilab - Vivian O'Dell, Stefano Rapisarda, Jon Kotcher, Jovan Mitrevski 2. MSU - Maris Abolins, Dan Edmunds (DE), Philippe Laurens 3. Northeastern - Ella Barberis 4. Saclay - Denis Calvet (DC), Jiri Bystricky Progress Reports 1. Denis Calvet (Saclay) - Single Channel ADF Card Document describing measurements and known problems has been circulated. To address the problems in the analog input - ADC section of the ADF card Denis has proposed four solutions: i. Change ADC - rejected as too late so it is not feasible ii. Change ADC driver - not available yet from manufacturer but promised soon iii. Bring -5V to current ADC driver iv. Change the voltage gains in the differential amplifier ADC chain. Measurements have been made and circulated and this may be the easiest solution to implement Other know concerns: * Common mode rejection * Noise * Drifts due to temperature and power supply fluctuations. Calculations have been made and circulated. The output drift is likely to be within the 1 LSB level. DE: Thank you for all the work in making measurements and disseminating the results. 2. Stefano Rapisarda (Fermilab) - A summary of the status of the Test Waveform Generator was presented. A summary of this can be found at: http://www-ese.fnal.gov/D0CAL_TWG/ 3. Dan Edmunds (MSU) - Dan summarized his work on learning about the ADF card and made a number of points: * Reference Supplies - used for controlling the pedestal and the ADC common mode input need to be low impedance at the operating frequency. A note will be sent to Denis. * Analog ADC Section - relative to the four solutions considered by Denis: stay with current ADC and driver. Don't hope for parts that don't exist. Adding the -5V is a clean solution, not sure it is easy to implement. The solution of attenuating after the differential amplifier looks OK so far. * Layout of ADF card - Would like to preserve the noise performance of the single channel test card. Digital noise is generated close to analog - ADC section on the real ADF board. The corner of this section is close to serializers. The analog bandwidth of ~ 300 Mhz is much too large signals of interest (<15 Mhz) and only serves to introduce noise. * Dan has moved the analog section of the ADF card onto his CAD system to try to generate a layout where the noise is minimized. If all the channels can be made to look identical then the problem is reduced to designing one of them optimally. This would be the standard unit cell. This idea would yield benefits in manufacturing and testing and in any re-work that may be needed. * It may be useful to have a second round of the single channel tests using a proposed unit cell layout. He could produce such a test card in a short period of time. * Finalizing the design of the analog - ADC section of the Saclay version #2 card would let them get started on this 2nd layout. It is this analog - ADC section where most of the changes are. * The design rules used by Saclay have to be understood by MSU. This includes via parameters, pad sizes etc. Comments on Dan's presentation by Denis Calvet. * The gain of the ADC driver can be reduced to 0.5 and it will be stable. However, we still have to take care of the common mode voltage problem. DE: That is not the part of the circuit I was thinking about. Independent of the common mode voltage problems this proposal is to change from using an attenuator in the line terminators (after the "Dean Capacitor") followed by a gain of 1 differential amplifier to instead using a straight 80 Ohm line terminator and increasing the input resistors to the differential amplifier to bring its gain down under one. DC: I'm concerned about the part that the differential amplifier input resistors play in the line termination. DE: I think that I can show that the terminations are equivalent and changing how this is done will simplify this part of the circuit. DC: The solution of bringing -5V onto the board is better than the solution of putting an attenuator at the output of the differential amplifier before the ADC input. At a cost of violating VME 64X standards, four auxiliary pins meant for 48 V power can be used for the -5V. Modifications to make a test using the current ADF board would be minimal, lift a single pin per differential amplifier and connect them to the backplane -5V source. DE: If the -5V can be brought to board then it is the best solution to the common mode voltage problems and has additional advantages. DC: Power ratings are not exceeded as we need 800 mA per ADF card or 16 Amps/crate. Doable with a single pin. The standard unit cell layout idea is attractive but, there are too many constraints on the board to make it practical. DE: It would be nice/essential to layout all channels in the analog ADC section the same way. DC: The new small board is a reasonable idea but, it does not necessarily prove that the layout will work in the full 32 channel ADF card. We must make the full board work. 4. Philippe Laurens (MSU) - Philippe reported on progress in porting Denis' code to MSU. MSU has been able to recompile and run the Windows version for the last few weeks. A Linux version of the code library used by the Saclay code for the OS-dependent operations was sent to MSU this Monday. This file was encrypted and PL wasn't sure of the motivation as DZero does not typically keep its source code private. PL asked if that would be a problem. DC stated that this Saclay code could be used and posted freely by DZero. Progress has been made in understanding the code structure and ADF card and firmware control from this test program. The prototype card was powered up and its FPGA's configured successfully. Need to know specifically which bitstream files to use from the CD that Saclay gave MSU. DC - Will give instructions on file. Directories with no suffix use Leonardo for synthesis, and files with suffix "_X" use Xilinx. DC migrated from Leonardo to Linux to conform with others. The makefiles were modified and the code was recompiled and linked on Linux with SBS-bit3 library. Have not yet ran this version as the bit3 documentation indicates that one needs to recompile the linux kernel. JM: No need to do this for a limited usage of the bit3 software. Simple modification of SBS-bit3 source code can avoid needing to rebuild the kernel. PL will check with JM to find out how to do this. 5. Jovan Mistrevski (Columbia) - Has just moved to Chicago and hence is out of touch with current state of things. A second TAB card is done and will arrive for next integration test. When? Delayed? GAB is in production after some financial issues were straightened out. Software for GAB is largely there. JM will go back to Nevis once GAB arrives as he will need to work with it. 6. Ella Barberis (Northeastern) - Gave an update on progress with simulation. Studies will be done with L1CTT, L1CAL, L1MUON modules but, not with full blown Trigsim for reasons of lack of manpower. Physics groups have been contacted with requests for assistance in getting Trigsim going. 7. Vivian O'Dell (Fermilab) - Questions were raised about current situation at UI-Chicago. No one had solid information on their position relative to the construction of the SCL interface card. Stefano has taken a preliminary look at it and Jovan opined that it was more complicated than the card they had constructed at Nevis and whoever would pick up this task would have to work closely with ADF card engineers. 8. Jiri Bystricky (Saclay) - presented a series of slides available at http://www-d0.fnal.gov/~bystri/noiseDac.ppt summarizing his analysis of pedestal noise data based on 13k measurements/channel sent by DE, and collected by the pedestal tuning program called "Find_DAC" which runs on TCC to calibrate the current L1CAL. After eliminating obvious bad channels, the histograms (in ET) were bi-modal in character representing the barrel and endcap calorimeters. Jon Kotcher (JK): Are the bad channels local, do they move? DE: All of the above. A few sparking channels are excluded from participation in the generation of L1 Triggers during Physics running. JK: Are they suppressed? DE: Two scenarios must be considered: does one read out the precision values and does one use a given tower in triggering. JK: If the trigger tower is bad does not that mean that the precision data making it up is compromised? DE: Not necessarily. The summer hybrids making up the trigger towers often go bad not affecting the underlying precision data. Noise Issues: DC: What is the minimum E (ET?) that one wants to see in a single tower? DE: EM Et and Total Et trigger thresholds of 3 GeV are used. The latter implies the an ET of 1.5 GeV in EM and 1.5 GeV in HAD are of interest. The goal is keep ADF card from contributing to the noise coming from BLS. This is ~1 LSB. DC: What is a good measure of noise performance? DE: Current system stays on a single bit like a rock. DC: Our single channel test shows ~5% of events outside single bit. With 32 channels on a card it has to be worse. DE: Need to optimize the layout so this is achievable. DC: Maybe this will not be possible. DE: This is not an option. We must reach this goal. DC: How stable is temperature in MCH? DE: Once equilibrium has been reached stability to within 2 deg-F is normal. One should also recognize that there are synchronous noise sources associated with the 132 ns clocking on the BLS cards. In Run I this synchronous noise on the BLS signals was as high as a few GeV but, was never a problem because it was absolutely constant cycle after cycle. In Run IIA the level of the synchronous noise is lower but it does not appear to be quite as constant. Other Issues JM: When will the next integration test take place? DE: Will be at lab toward end of next week. Right now time is usefully spent understanding ADF card layout. Will get together then to work on ADF card integration issues.