********************** 396 nsec Operation Dan Edmunds 29-Jan-04 ********************** Until now a lot of effort has gone into thinking about how to operate the new trigger with 132 nsec BX's in which case the ADF card had the challenging task of assigning Calorimeter energy depositions to the correct BX. The design of the ADF firmware contains special blocks to help with this, e.g. peak finding even when the ADC is saturated. The algorithms for 132 nsec running make use of ADC samples on the rising edge of the BLS signal, where there is good dV/dt but non optimal signal to noise ratio. It is now absolutely certain that 396 nsec BX's is the first type of Beam Physics Running that this new trigger will be used for. It is very likely (i.e. almost in writing) that 396 nsec BX's is the only type of running that this trigger will ever be used for. From the point of view of processing the raw ADC samples on the ADF card, I think it would be good to talk about the best way to handle 396 nsec operation. I would like to make sure that we do this while Denis is still able to spend time working on this project. - We know that with 396 nsec BX's that we will still need to step through the various stages of ADF/TAB/GAB processing at the full 132 nsec "tick rate". We need to do this to keep the latency of the new trigger within the required limits and we need to do this to maintain the already designed links between cards. - Is there some advantage in setting up the ADF so that, for the 2 out of every 3 ticks that do not have an associated real BX, the ADF will explicitly send to the TAB digital values that represent zero energy deposited in the Cal. If we do not do this then 2/3 of the processing in the TAB/GAB is going to be on miss-timed non real data. Looking at anything on a scope or logic analyzer or in a distribution of the overall output from the TAB/GAB will be harder because 2/3 of it is junk. Let's just make it explicit where the real BX's are, (we need to understand that anyway) and get rid of the 2/3 of the data that is junk and can hide the things we are looking for. - Filtering the raw ADC samples to make the best measurement of the energy deposited in the Calorimeter. This is the only game left in town for the ADF. Associating the energy deposit with the correct BX is no longer an issue (at all) with 396 nsec BX's. Raw ADC samples from the rising edge of the BLS signals are not good to use. This is because: They are not the samples with the best signal to noise ratio. On a given BLS Cable, the exact position of the BLS signal moves around from one energy deposit to the next. This effect is typically about +- 10 nsec. A lot of the BLS data that I have on the web shows this effect. On a given BLS Cable, for two energy deposits that result in equal peak amplitude BLS signals, the ADC samples that you make along the rising edge, at fixed times wrt to the BX, can vary a lot. Along the front edge the signals rise at about 1% of peak amplitude per nsec. Thus you can see the size of this effect. The best ADC samples to use in calculating the value of the energy deposit in the Cal are those from the peak of the BLS signal. These samples have the best signal to noise ratio. The peak of the BLS signal is rather broad and flat. Order of magnitude it remains above 95% of its peak value for about 150 nsec and above 90% of its peak amplitude for about 200 nsec. Obviously the peak is where the dV/dt is smallest so the problem of the BLS signals moving around by +- 10 nsec has the lease effect on these ADC samples. The BLS signal peak is wide enough to collect many raw ADC measurements. The ADC's on the ADF sample every 33 nsec. Averaging (filtering with coefficients) just the 5 raw ADC samples from around the peak of the BLS signal may be the best way to make a digital measurement of the energy deposition. Doing that may require a "non-trivial" change to the basic design of the ADF's filter. It is a "block diagram level change" because it means that the Input Decimator block goes away. On the other hand we would only be using 5 out of the 12 ADC samples that are taken every 396 nsec. The other 7 samples are out of BX time junk and can be immediately discarded. So with the current speed FPGA there must be a clean way to handle this, i.e. filter these 5 ADC samples and use the result from the filter for the tick that has the real BX. For the other 2 ticks in this 396 nsec cycle, output digital values that represent zero energy deposited. The filter itself only has to cycle once every 396 nsec but it must use 5 full speed raw ADC samples as its input. This is also a "block diagram level change" because the ADF would need to know the 396 nsec structure. Right now it just does the same thing every 132 nsec. But, there is no point in hiding from 396 - that is the real beam structure. All of the filtering talked about above (and all of the filtering that people have talked about in general so far) is effectively high frequency filtering. But if you look at the BLS signals on the web you also see low frequency noise. In the 200 nsec/div scope pictures you see some sloped base lines. In the study of BLS signals taken while the precision readout section of the BLS card is processing data you see small shifts in the base line. There is NO analog filtering before the ADC to remove low frequency noise (i.e. BLS signal components that are of such a low frequency that can not possibly be part of a real energy deposit BLS signal do get into the ADC's). The only low frequency cutoff is set by the "Dean Cap" and the 79 Ohm terminator. This RC is about 37 usec. An entire BLS signal "bump" lasts for only 1 usec. The long "Dean Cap" Terminator RC is for a purpose that has to do with delivering BLS signals to the trigger that are free from the effects of pile up. But it does let low frequency noise into the ADC's. To optimally convert raw ADC samples into energy deposit measurements we can gain some by removing this low frequency noise. People may want to think about doing the following kind of filtering for optimal 396 nsec operation: 132 nsec ticks ADF Data Sent to TAB for this tick -------------- ------------------------------------------- tick "N+4" digital value that represents zero energy tick "N+5" digital value that represents zero energy tick "N+6" digital value that is the difference between the filter output from the 5 raw ADC samples collected around the peak of the BLS signal assigned to tick "N+6" and the filter output from the 5 raw ADC samples collected around the peak of the BLS signal assigned to tick "N+3" tick "N+7" digital value that represents zero energy tick "N+8" digital value that represents zero energy tick "N+9" digital value that is the difference between the filter output from the 5 raw ADC samples collected around the peak of the BLS signal assigned to tick "N+9" and the filter output from the 5 raw ADC samples collected around the peak of the BLS signal assigned to tick "N+6" i.e. what the ADF sends to TAB is the difference between the best measurement of the current real BX and the best measurement of the real BX that happened 396 nsec ago. The electronics in the Cal precision readout system does effectively do this and filters out the low frequency noise. There are some big potential sources of low frequency noise, e.g. 2 Transrex's with SRC's growling away at 1000's of Amps, and recall that wrt mechanical vibration the Cal is the world's biggest capacitor microphone. - I think this is also an opportunity to think about what processing of the raw ADC signals do we want to be taking place in the ADF cards when we first start commissioning this trigger with real beam BLS signals. My strong feeling here is to keep it simple in the beginning. At the beginning of commissioning, doing complex processing of the raw ADC samples in the ADF card, is just a good way to get confused, waste time, and not see the obvious problems. I think that in the beginning commissioning work with real beam BLS signals, that a good way to setup the ADF would be for it to just use the one raw ADC sample from the point in time near the peak of the BLS signal as the measure of that BLS signal. If we can not make that work and understand all the problems (broken cables, things plugged in wrong, miss-timed ADC samples) then more complex processing of the raw ADC output is just going to confuse matters and slow down debugging. We should keep in mind that with 396 nsec BX's, fancy digital processing of the BLS signals is not going to make things that much better than just a single raw ADC sample. The one advantage that we can take of this 396 nsec BX's operation is to keep the system simple in the beginning to make it easier to debug.