RUN 2B L1CAL MEETING MINUTES 5 February, 2004 Present o Fermilab: M.Adams, D.Edmunds, J.Kotcher o MSU: M.Abolins, R.Brock, P.Laurens o Northeastern: D.Wood o Rice: P.Padley o Saclay: D.Calvet (by phone) Technicality: ------------- o This was the first L1CAL videoconference using an ip connection (instead of ISDN). There was significant initial confusion while everyone tried to connect. o The common number to connect to for this meeting appears at the very bottom of Sheila's confirmation message. o Is Hal still planning on forwarding the connection reminders to all participants for future meetings? ADF Status (D.Calvet, D.Edmunds) ---------- DC: o Continuing discussions with Dan Edmunds on revisions to ADF Card - e.g. one simplification removes a voltage reference - some of Dan's suggestions are easy to agree with - some need to be argued against o Continued testing with Single ADC Channel test board - added a negative 5 Volt supply voltage - understand how to implement this change in real system crate via the unused auxiliary 48V reserved pins o MSU should modify one or a few channels on the current Rev 1 prototype - including all known documented design changes - including adding an external -5V supply o Working on VHDL software test bench for SCLD o Reorganizing test software o Modifying Channel Link tester to be controlled from RS232 o Considering building a second instance of a Rev 1 prototype ADF - to allow further independent testing at Saclay - skipping some analog components to allow modifications DE: o Nice work on Single Channel Test - Good noise performance and good DC performance - Remaining issue is to successfully transfer to 32 channel layout o Sent another list of suggestions to Denis - Suggestions and items to discuss and document - Before signing off on all choices made o Agree to modify the Rev 1 prototype ADF card currently at MSU - Need one more phone conversation with Denis - Intend to do work on that next week DC: Second integration test should try and collect real energy deposit signal DE: Yes, and this should be done after some channel(s) have been modified - To look like, as much as possible, as the Revision 2 ADF analog front-end DE: Continued working on a layout for a unit cell of the analog section - Using MSU's Mentor Graphics layout software - Just solved some licensing issues - Nearly done and ready to extract results DC: That's good news. - Transfer back to Saclay's Cadence software will have to be done manually. - Component placement will be copied and the traces re-routed. DE: One of Dan's e-mail question was related to the allocation of IO pins on the FPGAs. - Massive amount of traces between Analog section and FPGA logic - Should try to reduce the number of vias and crisscrossing - Motivation is to lower induced noise - Try to produce the cleanest design, easiest to maintain DC: That's difficult in practice - No tool to easily go back and forth between place and route tools and schematic - Additional difficulty in communication between two people 200 m apart, and on two separate computing environments, namely Denis and the layout engineer. DE: Personal experience shows it is advantageous to put extra time up front to produce an understandable, ordered layout. DC: Optimizations were indeed made for the firmware - Control the routing inside the FPGA Optimizing board layout is much harder - Constrain oneself to same pinout and same firmware for all 4 FPGAs - Original pin allocation list was created by hand on paper - But routing issues, component sizes, space constraints - Channels had to be placed on both sides of the board - All these issues made the original scheme less optimal. - Improvement still a possibility DE: Totally agree with choices to have same FPGA firmware on all 4 sites - one site using extra logic which is repeated but unused on other sites The new proposed layout should help as the two-side issue will go away - this is a 4x4 matrix of unit cells - each EM/HD channel pair would thus be laid out identically - channels will no longer be assigned to one side or the other PP: When will the Revision 2 ADF Board be ready? DE: One needs to look at the total time between now and Summer 2005 installation. The assembling and testing of the ~100 boards will not be the dominant step. The important step is to produce a Rev 2 board that is optimized, easy to live with and maintain, with no routing issues, and fully tested. DC: There are only 3 or 4 layout engineers at Saclay to route the board (actually only 2 for complex designs like the ADF). They all have an input queue. It took 6 months to route the Rev 1 prototype. The current estimate is for one month of routing starting mid-February. DE: Is it possible to produce an "ASCII Net list", as fallback solution to bring the layout process to MSU? MSU: Online Software (P.Laurens) -------------------- o Continuing working with Saclay's test software o Ramping up on VHDL ADF firmware - Goal at the moment is to understand structure and location of elements - Slow and difficult process - Not expert on VHDL - Lots of files, including other board logic, and board level simulation o No success yet running test software on Linux - But didn't make this a high priority PP: Rice has enfineer with sbs-bit3-linux expertise, and will arrange contact. DE: MSU is submerging itself in the whole project, - Goal is to generate detailed documentation and specification - Part of the process of understanding all design aspects - Get ready to produce, maintain, and support the system. MSU will have a third engineer, Jason, - Will start later this spring - Already participating in meetings, - Already getting head start Nevis: No status report ------ o Jovan is at a Radiation Worker Training session Project Schedule ---------------- JK: What is the new target date for the second integration tests - 26 January date was missed DE: This was discussed in e-mail with Hal - Columbia still working with TAB board they would send for test - MSU current top priority is design changes with Saclay - This test is still needed before committing to any final Rev 2 layout - Best guess is 2 weeks from now DC: - Test is needed to verify ADF to TAB high speed link - Still need to collect samples of real Tevatron energy deposits DE: Rev 2 prototype schedule - "By definition" this is also the final design - First produce 5 or 10 units, enough to support testing: - Card to card noise tests - Multi crate tests - Several test sites: FNAL, MSU, Saclay - Target should be for testing new cards during summer 2004 - Goal is to sign off on producing the rest of the ~100 ADF cards DC: - Denis has little work to do for Rev 2 schematics - Bulk of the effort is in Rev 2 layout, which is not under Denis' control JK: The group should produce a revised inclusive schedule for all these steps - So that all groups can know how and when to participate - Need somebody to take charge of this coordination Cabling ------- DE: We should start tightening the understanding of detailed cabling of all signals through the whole system - From BLS to ADF, and from ADF to TAB - Including channel assignment on ADF, - Including ADF card assignment in crates - Partial specifications may already exists - Alan at UIC is already studying BLS to ADF cabling - Need to give Alan and others all constraints to work with - This may influence layout of Rev 2 ADF and should be finalized ASAP DW: Should we put a "straw man cable map" on the agenda for next meeting? Beam Crossing period (a.k.a. 396 ns) -------------------- DE: The Run IIb L1CAL project started with strong focus on 132 ns Beam Crossing - Main difficulty was to associate energy deposit with correct crossing No longer the case; - L1CAL cycle time will stay at 132ns, but bunches will be 396 ns apart - Emphasis should become to best trigger at 396 ns - Time resolution of energy deposits is no longer an issue - Focus needs to now switch to filtering and measuring amplitude The goal of this agenda item was not to have a live discussion today, but to invite everyone involved to start thinking about the implications. DC: Changing the firmware is a lot of work - Should not be made a priority at the moment - Would have to be done later in time Existing firmware has lots of built-in flexibility - e.g. passing raw data, using less coefficients, skipping peak detector - Should be sufficient to move forward Not convinced that digital filtering is truly no longer needed - Still see ~20% of previous Beam Crossing deposit 396ns later - This would not be an issue in current Run IIa L1CAL design - This may be an issue for the energy sums formed by Run IIb TABs - We would still see 20% of previous event DE: Agreed. We still need to recognize and address this fact: Past and current emphasis was 132ns, now needs to become 396 ns. Future Meeting Time ------------------- MA: No change yet in meeting schedule - Failed so far to find a better meeting time - We have reservations for this time slot through April 15