RUN 2B L1CAL MEETING MINUTES
                19 February, 2004

Present (apologies to those I left out due to lack of video)
o Fermilab:     M.Adams, M.Camuyrano, J.Kotcher, V.O'Dell, 
                S.Rapisarda, A.Stone
o MSU:          M.Abolins, R.Brock, D.Edmunds, P.Laurens, H.Weerts
o Nevis:        H.Evans
o Northeastern: E.Barberis
o Rice:         P.Padley



ADF Status (D.Edmunds)
----------

1) Power Supplies:
   - considering power sequencing issues. Still work to be done, but
     main issues with ADCs is now understood.

2) Moving from Analog desing to digital design
   - Channel Link
   - Timing/Control signal distribution from SCLD to 1 ADF to the rest
     of the ADFs across backplane (on reserved pins)
     . concern:clock fanouts driven directly by FPGA outputs -->
       reflections due to impedance mismatch, etc. ???
     . hasn't really been tested b/c needs the full 20 ADFs in the
       crate
     . Dan and Philippe have modelled this with capacitances
       representing cards
     . results on web - need to be looked at by Dan and Denis

o Task List to finish before ready to go to new layout
  - go back through list of changes that Dan and Denis have proposed
    to see which ones are necessary and which ones are only desirable
  - any items looming in the future
    . clock distribution on backplane: probably not good enough -
      needs more study
    . grounding pins on J0 connector (serial output)
    . shield on J0 connector - currently floating, should be grounded
    . Dan has only started with the digital section
  - tests still to do
    . long duration channel-link test: should be done at Fermilab
      > can take place in parallel with layout and results can be
        folded in
    . tests using prototype (1-channel) SCLD
  - starting date for layout of ADF v.2 moved at least to mid-March
    . layout should take approx. 2 months
    . this would mean mid-August for the integration test of the ADF
      v.2 at Fermilab

o Longer Term
  - over the summer, need to be able to run more than 1 ADF crate -->
    need multi-channel SCLD card

    
    
MSU: Online Software (P.Laurens)
--------------------

o Problems w/ Linux Bit-3 interface now solved
  - Linux now being used to do tests on ADF
  - some minor problems found with drivers - but nothing serious


Fermilab: TWG (S.Rapisarda)
-------------

o Working on finishing up the 2-channel system

o Starting the 32-Channel design
  - 6U form factor difficult for 32 channels (connector real estate)
  - 9U would be possible from point of view of end users (ADF testers)

          

Nevis: TAB/GAB (H.Evans)
-----------------------

o Assembled GAB prototype arrived at Nevis last week
  - has been powered up successfully, but functional testing has not
    yet started
  - will do this after tests of 2nd TAB
  - publicity pictures of the board will be posted on the web soon

o 2nd TAB prototype under test
  - want to finish this off so that we can send one TAB to Fermilab
    (permanently) for integration tests while keeping one at Nevis

o Integration
  - most urgent task from the TAB perspective is to check the G-link
    output to L2/L3. This is the last test before we can declare the
    board to be mechanically sound (and therefore ready for
    production.) Doing this quickly is important because TAB PCBs are
    sitting at Nevis growing old and should be assembled as soon as
    possible.
  - note: this test would disturb the running system. So should aim
    for next mini-shutdown in early March
    . will take fiber from TAB to one of the inputs of current system
      during 0-bias run
    . can easily do ascii dump of a few events, for more will need to
      look at L3 data (this is easy to produce - but may be difficult
      to look at).



   
Cabling (A.Stone & M.Camuyrano)
-------

o see presentation posted off of agenda
  - also see cabling spreadsheet (a copy is posted in the "Cabling"
    section of the L1Cal hardware pages)
    http://www.nevis.columbia.edu/~evans/l1cal/hardware/hardware.html

o Current cabling
  - each current rack contains cables for all phi's and 4 eta's

o Proposed New system
  - 4 ADF crates, each in its own rack
  - patch panels at positions of existing racks --> move existing
    cables as little as possible
  - some patch panels will send cables to different ADF racks
  - TAB crate in middle

o Alan and Mario need feedback on this. Please look over their
  speadsheet.

o Other Infrastructure Issues
  - power supplies for each crate
  - safety reviews


Schedule Issues (J.Kotcher)
---------------

o Layout of ADF
  - If at Saclay
    . how to monitor progress?
  - If at MSU
    . need to transfer as much of design as possible from Saclay to
      MSU
      > use schematics (as ascii netlist) to transfer design to Mentor
        Graphics used at MSU
      > note: there are so many design changes that we can't just
        re-use the old layout
  - Does it make sense to do this at MSU regardless?
    . this decision needs to be made in the next few weeks and must
      include Denis and others from Saclay
  - Tentatively set the date for this decision at 2nd week of March