RUN 2B L1CAL MEETING MINUTES 4 March, 2004 Present o Fermilab: J.Mitrevski, S.Rapisarda, H.Weerts o FSU: T.Adams o MSU: R.Brock, M.Abolins, P.Laurens o Nevis: H.Evans, C.Johnson o Northeastern: D.Wood o Rice: P.Padley o Saclay: Fermilab: TWG (S.Rapisarda) ------------- o Documentation - has been updated on the web o Software - preliminary USB interface tests to be used in 16 channels o Hardware - decide to make 16 channel board (32 doesn't fit in 6U) . can use two for 32 channels . can be synchronized - can use local clock and clock from SCL - improved RS232 speed (interface to MS EXcel spreadsheet) o In Progress - testing SCL triggering: particular BC number - still work to do on filtering o 2 Channel Board - this is basically ready for integration test - let Stefano know if there are any special requirements . in particular: what kind of triggering will be needed Nevis: TAB/GAB (H.Evans) ----------------------- o GAB prototype tests - have successfully read from various registers on the card, but main testing is waiting for tests of 2nd TAB o TAB prototype tests - have verified that 2nd TAB works as expected - started tests running 2 TABs simultaneously . initial results look good Cabling ------- o Comments on presentation by Alan and Mario last meeting? - please send to the UIC group ADF/SCLD Status (P.Laurens) --------------- o MSU will do the layout of the ADF v.2 - enter schematic as netlist input to Mentor - Making extensive use of "unit cells" . analog, adc's, fpga's, power, etc. - will need a tool to instantiate unit cells multiple times from single templates . most templates are already generated . 1st implementation of tool has been made - will make a trial next week of putting this into the layout software o This will allow Saclay to resume design/production of SCLD - MSU needs to be closely coupled to this design - plan for long-term maintenance of this card needs to be decided - should make sure that schematics/layout done with a tool that is usable by the group that will take up the long-term responsibility for this board o VME FPGA on ADF - current chip (Cypress) is no longer produced - note: only need A24:D16 for ADF - will replace this with an FPGA using our own interface o Also need to understand the SCL interface on the backplane o High-speed clock over backplane - prelim measurements indicate that this might not work - should have alternatives by next week MSU: Online Software (P.Laurens) -------------------- o Mainly concentrating on ADF redesign in last few weeks, but have continued to use new Linux drivers for ADF tests Integration Test Goals ---------------------- o See file posted off of agenda for full list o Next round of tests slated to start during mini-shutdown - approx. March 15-24 - note: tests will probably extend over more than 10 days o Discussion of GOALS (more details off agenda page) - very important to minimize the amount of time that Dan/Philippe/Denis are taken away from the ADF design to do this 1. Learn how to run the single channel SCLD card. 2. Long duration Channel Link test. 3. Capture some BLS signal with the ADF card. - this needs real data with the Tevatron running 4. Have MSU people get more experience working with ADF-1 and the control software for it. 5. Test transmission of data to L2/L3 using G-Link optical transmitter. - only time that this can be done is when D0 is not running ==> has to be done during the shutdown - involves taking apart some aspects of current readout to incorporate Run IIb L1Cal . replace an input fiber to the existing VRB(s) with Run IIb L1Cal output . needs to be put back together at the end - need to understand unpacking of L3 data . Todd Adams is thinking about unpacking and examines . data we take will be useful for this 6. Test of analog signal transmission through cable harness - this would be a part of test 3. - note: Denis has checked cross-talk on inputs using 2-Channel TWG . no problems were found here