RUN 2B L1CAL MEETING MINUTES
                25 March, 2004

Present 
o Fermilab:     T.Adams, D.Edmunds, P.Laurens, J.Mitrevski, 
		V.O'Dell, S.Rapisarda, H.Weerts
o MSU:          M.Abolins
o Nevis:        H.Evans, C.Johnson
o Rice:         P.Padley
o Saclay:       D.Calvet, E.Perez



Fermilab: TWG (S.Rapisarda)
-------------

o Software
  - no changes

o Hardware
  - SCL triggering implemented
    . can trigger on specific BX/TURN
    . enough memory to cover several TURNs (292 BC's)
  - External (push button) trigger
  - Software generated trigger

o Work in Progress
  - software chages for SCL triggering/expanded memory

o When will the TWG be needed?
  - main function: used to test individual ADF cards at MSU
  - timescale for this is the summer
          

Nevis: TAB/GAB (H.Evans)
-----------------------

o GAB prototype tests
  - writing online code for GAB tests

o TAB prototype tests
  - tested G-Link output (L2/L3) with test card
    . found that local oscillator on TAB (same as in SCLR) is not
      stable enough to drive the G-Link output successfully
    . using an HP waveform generator we were able to get a jitter-free
      clock 
  - signal lock was achieved using G-Link output from TAB to small
    G-Link receiver test card.
    . No data verification is possible with this card.



ADF/SCLD Status (D.Calvet)
---------------

o SCLD: Design finished, schematics made
  - layout will start soon

o ADF v1/v2
  - have sent 2nd ADF v1 PCB for assembly - should receive back in a
    few weeks 
  - have documented all changes between the ADF v1 and v2
    . Dan and Denis will use this document to make sure nothing is
      missed 

o VME Interface Re-design
  - slides linked off agenda
  - problem is: Cypress bridge chip is now obsolete
  - have re-designed to get rid of Cypress chip
  - Benefits
    . design is simpler - less parts
    . easier to maintain - no obsolete parts
    . does not depend on Cypress software anymore
    . new design is cheaper
  - have validated this design in simulation
    
    
Online Software (P.Laurens)
---------------

o mainly working on recompiling firmware
  - next step is to download this to SCLD/ADF


Offline Software (T.Adams)
----------------

o have modified STT unpacking code to do hex dumps of existing L1Cal
  code (from crate 10)
  - this has been tested with current L1Cal crate

o In the long term - how will we unpack the data
  - IOgen or something else?
  - Philippe has written code to unpack existing L1Cal
    . has lots of sanity-checks, etc.
  - Todd will pursue this



Integration Test Status (J.Mitrevski)
-----------------------

o Last night: could send data from TAB to VRB (in current L1Cal)
  - used Philippe's software to dump data from VRB
    . sent to a log file
    . trivial to write this out to L3 now
  - G-link claims no loss of synch
  - Header and Parity are fine, Data is always 0
  - data = 0 is probably a TAB firmware issue
    . also 0 in TAB output memories
  - a handful of events tried

o To Do
  1) track down firmware problem that makes data = 0
  2) can write out data to L3 between stores
    . need to clean up a few things first
    . quite simple to do if read out full crate
    . requires some simple changes to only read out VRB channel
      corresponding to TAB



Data from Splitters: How much do we need?
----------------------------------------

o See description on agenda page

o Using ADF test memory (128 BCs)
  - allows to test whether system does the right thing
  - can also load real events into ADF test memory and compare with
    existing L1Cal and/or simulator
  - this also allows to "stress test" the system by loading
    particularly problematic events

o Digital Filter coeff. determination
  - one possibility is to "turn off" filtering at the beginning
    . this keeps everything simple  
  - will also use splitters before installation to mainly test the
    mechanism for determining filter coeff's
  - note: total benefit from "optimal" filtering scheme will be fairly
    small 
    . this was necessary at 132 ns, but not so important at 396 ns
    . can see this now by looking at current L1Cal vs. precision
      readout 

o How many channels do we have to test before turning on?
  - want to be able to say that we understand efficiencies,
    etc. before turning on
  - can run simulator on current L1Cal data

o Decisions
  1) Need to produce a coherent plan for testing the system before
     turn-on
     . Hal will produce a first try at this for next meeting
     . everyone should send their thoughts to him about this
  2) Do *not* produce more splitters