RUN 2B L1CAL MEETING MINUTES
                   6 May, 2004

Present 
o Fermilab      M.Adams, T.Adams, J.Mitrevski, S.Rapisarda, W.Taylor,
		H.Weerts
o MSU           D.Edmunds, P.Laurens
o Nevis         H.Evans
o Saclay        J.Bystricky, D.Calvet, E.Perez


Nevis: TAB/GAB (H.Evans)
--------------

o TAB/GAB prototype tests
  - continue work on long term TAB-to-GAB data transmission tests
  - B.E.R. < 1e-13 (no errors observed so far)
  - will continue pushing on this
  - try to generate "pathological" data

o L2/L3 readout tests will continue next week
  - assuming we squeeze in some time between runs



Fermilab: TWG (S.Rapisarda)
-------------

o Working on spec of 32-channel board
  - may be able to put this on a double-wide 6U board

          

MSU: ADF (D.Edmunds)
--------

o Continuing work on getting design ready for ADF v.2
  - have mainly moved to layout phase

o Have started writing a document about how ADF cards will be tested
  - note: will probably need to use a Channel Link test card (Saclay's
    or Nevis'?)


Saclay: ADF (D.Calvet)
-----------

o see slides linked off agenda

o B.E.R. measurement of Channel Link Tester
  - Measuring ber at 448 MHz
  - using Channel Link Test Card
  - send pseudo-random data or fixed data pattern

o Summary (using scope)
  - eye pattern is nicely open
  - ber < 1e-15 for all cable pairs
  - operates correctly w/ and w/out DC balancd and DeSkew

o Summary (using data capture on Channel Link Tester)
  - ber < 3e-14 for one link (no xmit errors)
    . link run for 40 hours
  - tests continuing

o Further Validation Tests
  - operate 1 ADF w/ clock from SCLD
  - operate 2 ADFs w/ clock from SCLD
  - meas. signal on TAB side ==> influence of TAB termination
  - determine optimum pre-emphasis level
  - check data on TAB side during extended test run period
    . note that this was not completely tested in Oct.03 integration
    . ADF can send constant, pseudo-random, pre-stored data patterns
    . TAB can count parity errors
    . but should really do a bit-by-bit comparison of the data as it
      arrives - particularly pseudo-random

o When to do the data transfer test?
  - also need to do TAB L2/L3 readout tests

o SCLD: layout finished - in final checks
  - go to production next week or week after
  - will prod. 2 PCBs, cable one
  - test at Saclay then send to Fermilab
    

Online Software (P.Laurens)
---------------

o Philippe is concentrating mainly on the ADF work


Offline Software (T.Adams)
----------------

o Todd has been talking with Philippe about existing code
  - will use this as a basis to make a new class



Simulation (E.Barberis)
----------

o Simulation workshop on May 11



UIC: Cabling (A.Stone)
------------

o see summary linked off agenda page



Pre-Installation Responsibilities (H.Evans)
---------------------------------

o see tentative list linked off agenda
  - also note new "Installation" web pages off of main L1Cal page

o Please send comments to Hal as soon as possible
  - we need to have this completely clarified by Fresno