RUN 2B L1CAL MEETING MINUTES
                   1 July, 2004

Present 
o Fermilab      D.Edmunds, J.Mitrevski, S.Rapisarda, W.Taylor, N.Varelas
o MSU           J.Biehl
o Nevis         H.Evans, J.Parsons
o Saclay        D.Calvet


Fermilab: TWG (S.Rapisarda)
-------------

o Stefano and Dan are looking at commercial equipment
  - Agilent is a possibility (single channel)
  - will also need a multiplexer/switch card to allow 32-channel,
    differential operation
    . commercial solutions to this are rather expensive
    . may need to make a simple card to do this


Nevis: TAB/GAB (H.Evans)
--------------

o TAB/GAB crate
  - 2nd backplane being assembled
  - will repair short in 1st backplane when 2nd is finished
  - currently running TAB-->GAB tests using crate w/ 1st backplane
    . avoiding bad slot
o TAB/GAB firmware
  - updating some TAB firmware to aid in system simulation
  - will start coding a few example and/or terms as soon as this is
    done 
    . timescale = a few weeks


Saclay: ADF/SCLD (D.Calvet)
----------------

o SCLD received last week
o 1st tests
  - firmware downloaded by Jtag and by prom
  - a few minor errors found and corrected
  - using 1-channel firmware, have tested board with ADF at Saclay
    ==> ok
    . have sync'ed ADF w/ onboard oscillator and checked communication
o Next steps
  - systematically check output signals
o Plan: after board is validated will send to Dan
  - Dan will check with ADF v2
  - after that will make a 2nd SCLD
  - should think about whether we need a 3rd board
    . this will require making a new PCB and ordering more components
o Have received documentation from Dan about changes in use of SCLD
  signals in ADF v2
  - will mainly require some simple changes - termination resistors
  - one pair used as single-ended signals (cable-connect) will require
    more thought
    . Denis and Dan will discuss possibilities here 
  - generally: should not be difficult to make SCLD compatible with
    ADF v2



MSU: ADF (D.Edumnds)
--------

o Work continuing on board layout
o 3 Issues remaining
  1) LEDs on front panel
  2) debug connectors: could expand their uses
  3) front panel Jtag: should not be needed, but may be useful
o Board control firmware being written
o Software work
  - writing Python code to do interfacing with Denis' code
o Error signals from ADF
  - in ADF v2 there is no SCL error information directly from the ADF
    . no need for this because of the simplicity of the state machine
      (i.e. there is only one state)
  - will still be monitored every 5 sec by TCC
    . can use this to flag problems in the card
o System Synchronization: aligning data for all channels to same BC
  - trigger end of BLS cable: spread ~ 100 ns (cable length, etc.)
    . note this changes by ~15 ns event-by-event
    . but analog signal remains >90% of max for 3-4 ADC samples
  - will realign this in ADF
    . channel-by-channel deskewing times will not change from current
      system (available on the web)
  - also send tick number of BC that produced data to TAB


UIC: Cabling (N.Varelas)
------------

o Discussions continuing with Johnny Green about patch panel
  - "drawer design": need slack in cables for this to move
o Have received a few of the "pleated-foil" cables
o Will try to make first tests with a chain containing an example of
  all components ~next week
  - prototype still on track for mid-August



Northeastern: Simulation (E.Barberis)
------------------------

o Next simulation workshop: July 14


Test Area
---------

o Still waiting for a time when Dan is at Fermilab and there is some
  accelerator downtime to do these tests
  a) TAB --> L3 --> tape
     . perhaps tomorrow
  b) ADF --> TAB long-term tests
     - some TAB firmware has to be changed for this
       > ~1 day by Jovan